Architecture and Advanced Electronics Pathways Toward Highly Adaptive Energy- Efficient Computing

With the explosion of the number of compute nodes, the bottleneck of future computing systems lies in the network architecture connecting the nodes. Addressing the bottleneck requires replacing current backplane-based network topologies. We propose to revolutionize computing electronics by realizing embedded optical waveguides for onboard networking and wireless chip-to-chip links at 200-GHz carrier frequency connecting neighboring boards in a rack. The control of novel rate-adaptive optical and mm-wave transceivers needs tight interlinking with the system software for runtime resource management

In materia implementation strategies of physical reservoir computing with memristive nanonetworks

Physical reservoir computing (RC) represents a computational framework that exploits information-processing capabilities of programmable matter, allowing the realization of energy-efficient neuromorphic hardware with fast learning and low training cost. Despite self-organized memristive networks have been demonstrated as physical reservoir able to extract relevant features from spatiotemporal input signals, multiterminal nanonetworks open the possibility for novel strategies of computing implementation. In this work, we report on implementation strategies of in materia RC with self-assembled memristive networks. Besides showing the spatiotemporal information processing capabilities of self-organized nanowire networks, we show through simulations that the emergent collective dynamics allows unconventional implementations of RC where the same electrodes can be used as both reservoir inputs and outputs. By comparing different implementation strategies on a digit recognition task, simulations show that the unconventional implementation allows a reduction of the hardware complexity without limiting computing capabilities, thus providing new insights for taking full advantage of in materia computing toward a rational design of neuromorphic systems

Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture

The key characteristics of the next generation of ICs for wearable applications include high integration density, small area, low power consumption, high energy-efficiency, reliability and enhanced mechanical properties like stretchability and transparency. The proper mix of new materials and novel integration strategies is the enabling factor to achieve those design specifications. Moving toward this goal, we introduce a graphene-based regular logic-array structure for energy efficient digital computing. It consists of graphene p-n junctions arranged into a regular mesh. The obtained structure resembles that of Programmable Logic Arrays (PLAs), hence the name Graphene-PLAs (GPLAs); the high expressive power of graphene p-n junctions and their resistive nature enables the implementation of ultra-low power adiabatic logic circuits

Using inductive Energy Participation Ratio for Superconducting Quantum Chip Characterization

We have developed an inductive energy participation ratio (iEPR) method and a concise procedure for superconducting quantum chip layout simulation and verification that is increasingly indispensable in large-scale, fault-tolerant quantum computing. It can be utilized to extract the characteristic parameters and the bare Hamiltonian of the layout in an efficient way. In theory, iEPR sheds light on the deep-seated relationship between energy distribution and representation transformation. As a stirring application, we apply it to a typical quantum chip layout, obtaining all the crucial characteristic parameters in one step that would be extremely challenging through the existing methods. Our work is expected to significantly improve the simulation and verification techniques and takes an essential step toward quantum electronic design automation

Toward sustainable data centers: a comprehensive energy management strategy

Data centers are major contributors to the emission of carbon dioxide to the atmosphere, and this contribution is expected to increase in the following years. This has encouraged the development of techniques to reduce the energy consumption and the environmental footprint of data centers. Whereas some of these techniques have succeeded to reduce the energy consumption of the hardware equipment of data centers (including IT, cooling, and power supply systems), we claim that sustainable data centers will be only possible if the problem is faced by means of a holistic approach that includes not only the aforementioned techniques but also intelligent and unifying solutions that enable a synergistic and energy-aware management of data centers. In this paper, we propose a comprehensive strategy to reduce the carbon footprint of data centers that uses the energy as a driver of their management procedures. In addition, we present a holistic management architecture for sustainable data centers that implements the aforementioned strategy, and we propose design guidelines to accomplish each step of the proposed strategy, referring to related achievements and enumerating the main challenges that must be still solved.Peer ReviewedPostprint (author's final draft