Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Sigma-Delta control of charge trapping in heterogeneous devices

Dielectric charging represents a major reliability issue in a variety of semiconductor devices. The accumulation of charge in dielectric layers of a device often alters its performance, affecting its circuital features and even reducing its effective lifetime. Although several contributions have been made in order to mitigate the undesired effects of charge trapping on circuit performance, dielectric charge trapping still remains an open reliability issue in several applications. The research work underlying this Thesis mainly focuses on the design, analysis and experimental validation of control strategies to compensate dielectric charging in heterogeneous devices. These control methods are based on the application of specifically designed voltage waveforms that produce complementary effects on the charge dynamics. Using sigma-delta loops, these controls allow to set and maintain, within some limits, the net trapped charge in the dielectric to desired levels that can be changed with time. This allows mitigating long-term reliability issues such as capacitance-voltage (C-V) shifts in MOS and MIM capacitors. Additionally, the bit streams generated by the control loops provide real-time information on the evolution of the trapped charge. The proposed controls also allow compensating the effects of the charge trapping due to external disturbances such as radiation. This has been demonstrated experimentally with MOS capacitors subjected to various types of ionizing radiation (X-rays and gamma rays) while a charge control is being applied. This approach opens up the possibility of establishing techniques for active compensation of radiation-induced charge in MOS structures as well as a new strategy for radiation sensing. A modeling strategy to characterize the dynamics of the dielectric charge in MOS capacitors is also presented. The diffusive nature of the charge trapping phenomena allows their behavioral characterization using Diffusive Representation tools. The experiments carried out demonstrate a very good matching between the predictions of the model and the experimental results obtained. The time variations in the charge dynamics due to changes in the volatges applied and/or due to external disturbances have been also investigated and modeled. Moreover, the charge dynamics of MOS capacitors under sigma-delta control is analyzed using the tools of Sliding Mode Controllers for an infinite sampling frequency approximation. A phenomenological analytical model is obtained which allows to predict and analyze the sequence of control signals. This model has been successfully validated with experimental data. Finally, the above control strategies are extended to other devices such as eMIM capacitors and perovskite solar cells. Preliminary results including open loop and closed loop control experiments are presented. These results demonstrate that the application of the controls allows to set and stabilize both the C-V characteristic of an eMIM capacitor and the current-voltage characteristic (J-V) of a perovskite solar cell.La carga atrapada en dieléctricos suele implicar un problema importante de fiabilidad en muchos dispositivos semiconductores. La acumulación de dicha carga, normalmente provocada por las tensiones aplicadas durante el uso del dispositivo, suele alterar el rendimiento de éste con el tiempo, afectar sus prestaciones a nivel de circuital e, incluso, reducir su vida útil. Aunque durante años se han realizado muchos trabajos para mitigar sus efectos no deseados, sobre todo a nivel circuital, la carga atrapada en dieléctricos sigue siendo un problema abierto que frena la aplicabilidad práctica de algunos dispositivos. El trabajo de investigación realizado en esta Tesis se centra principalmente en el diseño, análisis y validación experimental de estrategias de control para compensar la carga atrapada en dieléctricos de diversos tipos de dispositivos, incluyendo condensadores MOS, condensadores MIM fabricados con nanotecnología y dispositivos basados en perovskitas. Los controles propuestos se basan en utilizar formas de onda de tensión, específicamente diseñadas, que producen efectos complementarios en la dinámica de la carga. Mediante el uso de lazos sigma-delta, estos controles permiten establecer y mantener, dentro de unos límites, la carga neta atrapada en el dieléctrico a valores prefijados, que pueden cambiarse con el tiempo. Esto permite mitigar problemas de fiabilidad a largo plazo como por ejemplo las derivas de la curva capacidad-tensión (C-V) en condensadores MOS y MIM. Adicionalmente, las tramas de bits generadas por los lazos de control proporcionan información en tiempo real sobre la evolución de la carga. Los controles propuestos permiten también compensar los efectos de la carga atrapada en dieléctricos debida a perturbaciones externas como la radiación. Esto se ha demostrado experimentalmente con condesadores MOS sometidos a diversos tipos de radiación ionizante (rayos X y gamma) mientras se les aplicaba un control de carga. Este resultado abre la posibilidad tanto de establecer técnicas de compensación activa de carga inducida por radiación en estructuras MOS, como una nueva estrategia de sensado de radiación. Se presenta también una estrategia de modelado para caracterizar la dinámica de la carga dieléctrica en condensadores MOS. La naturaleza difusiva de los fenómenos de captura y eliminación de carga en dieléctricos permite caracterizar dichos fenómenos empleando herramientas de Representación Difusiva. Los experimentos realizados demuestran una muy buena correspondencia entre las predicciones del modelo y los resultados experimentales obtenidos. Se muestra también como las variaciones temporales de los modelos son debidas a cambios en las formas de onda de actuación del dispositivo y/o a perturbaciones externas. Además, la dinámica de carga en condensadores MOS bajo control sigma-delta se analiza utilizando herramientas de control en modo deslizante (SMC), considerando la aproximación de frecuencia de muestreo infinita. Con ello se obtiene un modelo analítico simplificado que permite predecir y analizar con éxito la secuencia de señales de control. Este modelo se ha validado satisfactoriamente con datos experimentales. Finalmente, las estrategias de control anteriores se han extendido a otros dispositivos susceptibles de sufrir efectos de carga atrapada que pueden afectar su fiabilidad. Así, se han llevado a cabo experimentos preliminares cuyos resultados demuestran que la aplicación de controles de carga permite controlar y estabilizar la característica C-V de un condensador eMIM y la característica corriente-tensión (J-V) de una célula solar basada en perovskitas.Postprint (published version

Enhanced Radiation-Induced Narrow Channel Effects in Commercial 0.18 μm Bulk Technology

Total ionizing dose effects are investigated in input/output transistors that are fabricated by using a commercial 0.18 μm bulk process. An enhanced radiation-induced narrow channel effect is demonstrated in N-type metal-oxide semiconductor (NMOS) and P-type metal-oxide semiconductor (PMOS) transistors, leading to a significant threshold voltage shift which may compromise circuit operations. Calculations using a code dedicated to radiation-induced charge trapping in oxides show that the radiation-induced positive charge trapping in trench oxides leads to the modifications of the electrical characteristics experimentally evidenced. Radiation hardening issues are finally discussed as a function of the device geometry and design

Study of Radiation Tolerant Storage Cells for Digital Systems

Single event upsets (SEUs) are a significant reliability issue in semiconductor devices. Fully Depleted Silicon-on-Insulator (FDSOI) technologies have been shown to exhibit better SEU performance compared to bulk technologies. This is attributed to the thin Silicon (Si) layer on top of a Buried Oxide (BOX) layer, which allows each transistor to function as an insulated Si island, thus reducing the threat of charge-sharing. Moreover, the small volume of the Si in FDSOI devices results in a reduction of the amount of charge induced by an ion strike. The effects of Total Ionizing Dose (TID) on integrated circuits (ICs) can lead to changes in gate propagation delays, leakage currents, and device functionality. When IC circuits are exposed to ionizing radiation, positive charges accumulate in the gate oxide and field oxide layers, which results in reduced gate control and increased leakage current. TID effects in bulk technologies are usually simpler due to the presence of only one gate oxide layer, but FDSOI technologies have a more complex response to TID effects because of the additional BOX layer. In this research, we aim to address the challenges of developing cost-effective electronics for space applications by bridging the gap between expensive space-qualified components and high-performance commercial technologies. Key research questions involve exploring various radiation-hardening-by-design (RHBD) techniques and their trade-offs, as well as investigating the feasibility of radiation-hardened microcontrollers. The effectiveness of RHBD techniques in mitigating soft errors is well-established. In our study, a test chip was designed using the 22-nm FDSOI process, incorporating multiple RHBD Flip-Flop (FF) chains alongside a conventional FF chain. Three distinct types of ring oscillators (ROs) and a 256 kbit SRAM was also fabricated in the test chip. To evaluate the SEU and TID performance of these designs, we conducted multiple irradiation experiments with alpha particles, heavy ions, and gamma-rays. Alpha particle irradiation tests were carried out at the University of Saskatchewan using an Americium-241 alpha source. Heavy ion experiments were performed at the Texas A&M University Cyclotron Institute, utilizing Ne, Ar, Cu, and Ag in a 15 MeV/amu cocktail. Lastly, TID experiments were conducted using a Gammacell 220 Co-60 chamber at the University of Saskatchewan. By evaluating the performance of these designs under various irradiation conditions, we strive to advance the development of cost-effective, high-performance electronics suitable for space applications, ultimately demonstrating the significance of this project. When exposed to heavy ions, radiation-hardened FFs demonstrated varying levels of improvement in SEU performance, albeit with added power and timing penalties compared to conventional designs. Stacked-transistor DFF designs showed significant enhancement, while charge-cancelling and interleaving techniques further reduced upsets. Guard-gate (GG) based FF designs provided additional SEU protection, with the DFR-FF and GG-DICE FF designs showing zero upsets under all test conditions. Schmitt-trigger-based DFF designs exhibited improved SEU performance, making them attractive choices for hardening applications. The 22-nm FDSOI process proved more resilient to TID effects than the 28-nm process; however, TID effects remained prominent, with increased leakage current and SRAM block degradation at high doses. These findings offer valuable insights for designers aiming to meet performance and SER specifications for circuits in radiation environments, emphasizing the need for additional attention during the design phase for complex radiation-hardened circuits