810 research outputs found
Evolutionary Synthesis of Cube Root Computational Circuit Using Graph Hybrid Estimation of Distribution Algorithm
The paper is focused on evolutionary synthesis of analog circuit realization of cube root function using proposed Graph Hybrid Estimation of Distribution Algorithm. The problem of cube root function circuit realization was adopted to demonstrate synthesis capability of the proposed method. Individuals of the population of the proposed method which represent promising topologies are encoded using graphs and hypergraphs. Hybridization with local search algorithm was used. The proposed method employs univariate probabilistic model
Evolutionary Synthesis of Analog Electronic Circuits Using EDA Algorithms
DisertaÄnĂ prĂĄce je zamÄĆena na nĂĄvrh analogovĂœch elektronickĂœch obvodĆŻ pomocĂ algoritmĆŻ s pravÄpodobnostnĂmi modely (algoritmy EDA). PrezentovanĂ© metody jsou na zĂĄkladÄ poĆŸadovanĂœch charakteristik cĂlovĂœch obvodĆŻ schopny navrhnout jak parametry pouĆŸitĂœch komponent tak takĂ© jejich topologii zapojenĂ. TĆi rĆŻznĂ© metody vyuĆŸitĂ EDA algoritmĆŻ jsou navrĆŸeny a otestovĂĄny na pĆĂkladech skuteÄnĂœch problĂ©mĆŻ z oblasti analogovĂœch elektronickĂœch obvodĆŻ. PrvnĂ metoda je urÄena pro nĂĄvrh pasivnĂch analogovĂœch obvodĆŻ a vyuĆŸĂvĂĄ algoritmus UMDA pro nĂĄvrh jak topologie zapojenĂ tak takĂ© hodnot parametrĆŻ pouĆŸitĂœch komponent. Metoda je pouĆŸita pro nĂĄvrh admitanÄnĂ sĂtÄ s poĆŸadovanou vstupnĂ impedancĂ pro ĂșÄely chaotickĂ©ho oscilĂĄtoru. DruhĂĄ metoda je takĂ© urÄena pro nĂĄvrh pasivnĂch analogovĂœch obvodĆŻ a vyuĆŸĂvĂĄ hybridnĂ pĆĂstup - UMDA pro nĂĄvrh topologie a metodu lokĂĄlnĂ optimalizace pro nĂĄvrh parametrĆŻ komponent. TĆetĂ metoda umoĆŸĆuje nĂĄvrh analogovĂœch obvodĆŻ obsahujĂcĂch takĂ© tranzistory. Metoda vyuĆŸĂvĂĄ hybridnĂ pĆĂstup - EDA algoritmus pro syntĂ©zu topologie a metoda lokĂĄlnĂ optimalizace pro urÄenĂ parametrĆŻ pouĆŸitĂœch komponent. Informace o topologii je v jednotlivĂœch jedincĂch populace vyjĂĄdĆena pomocĂ grafĆŻ a hypergrafĆŻ.Dissertation thesis is focused on design of analog electronic circuits using Estimation of Distribution Algorithms (EDA). Based on the desired characteristics of the target circuits the proposed methods are able to design the parameters of the used components and theirs topology of connection as well. Three different methods employing EDA algorithms are proposed and verified on examples of real problems from the area of analog circuits design. The first method is capable to design passive analog circuits. The method employs UMDA algorithm which is used for determination of the parameters of the used components and synthesis of the topology of their connection as well. The method is verified on the problem of design of admittance network with desired input impedance function which is used as a part of chaotic oscillator circuit. The second method is also capable to design passive analog circuits. The method employs hybrid approach - UMDA for synthesis of the topology and local optimization method for determination of the parameters of the components. The third method is capable to design analog circuits which include also ac- tive components such as transistors. Hybrid approach is used. The topology is synthesized using EDA algorithm and the parameters are determined using a local optimization method. In the individuals of the population information about the topology is represented using graphs and hypergraphs.
Analog layout design automation: ILP-based analog routers
The shrinking design window and high parasitic sensitivity in the advanced technology have imposed special challenges on the analog and radio frequency (RF) integrated circuit design. In this thesis, we propose a new methodology to address such a deficiency based on integer linear programming (ILP) but without compromising the capability of handling any special constraints for the analog routing problems. Distinct from the conventional methods, our algorithm utilizes adaptive resolutions for various routing regions. For a more congested region, a routing grid with higher resolution is employed, whereas a lower-resolution grid is adopted to a less crowded routing region. Moreover, we strengthen its speciality in handling interconnect width control so as to route the electrical nets based on analog constraints while considering proper interconnect width to address the acute interconnect parasitics, mismatch minimization, and electromigration effects simultaneously. In addition, to tackle the performance degradation due to layout dependent effects (LDEs) and take advantage of optical proximity correction (OPC) for resolution enhancement of subwavelength lithography, in this thesis we have also proposed an innovative LDE-aware analog layout migration scheme, which is equipped with our special routing methodology. The LDE constraints are first identified with aid of a special sensitivity analysis and then satisfied during the layout migration process. Afterwards the electrical nets are routed by an extended OPC-inclusive ILP-based analog router to improve the final layout image fidelity while the routability and analog constraints are respected in the meantime. The experimental results demonstrate the effectiveness and efficiency of our proposed methods in terms of both circuit performance and image quality compared to the previous works
Low-power adaptive control scheme using switching activity measurement method for reconfigurable analog-to-digital converters
Power consumption is a critical issue for portable devices. The ever-increasing demand for multimode wireless applications and the growing concerns towards power-aware green technology make dynamically reconfigurable hardware an attractive solution for overcoming the power issue. This is due to its advantages of flexibility, reusability, and adaptability. During the last decade, reconfigurable analog-to-digital converters (ReADCs) have been used to support multimode wireless applications. With the ability to adaptively scale the power consumption according to different operation modes, reconfigurable devices utilise the power supply efficiently. This can prolong battery life and reduce unnecessary heat emission to the environment. However, current adaptive mechanisms for ReADCs rely upon external control signals generated using digital signal processors (DSPs) in the baseband. This thesis aims to provide a single-chip solution for real-time and low-power ReADC implementations that can adaptively change the converter resolution according to signal variations without the need of the baseband processing. Specifically, the thesis focuses on the analysis, design and implementation of a low-power digital controller unit for ReADCs. In this study, the following two important reconfigurability issues are investigated: i) the detection mechanism for an adaptive implementation, and ii) the measure of power and area overheads that are introduced by the adaptive control modules. This thesis outlines four main achievements to address these issues. The first achievement is the development of the switching activity measurement (SWAM) method to detect different signal components based upon the observation of the output of an ADC. The second achievement is a proposed adaptive algorithm for ReADCs to dynamically adjust the resolution depending upon the variations in the input signal. The third achievement is an ASIC implementation of the adaptive control module for ReADCs. The module achieves low reconfiguration overheads in terms of area and power compared with the main analog part of a ReADC. The fourth achievement is the development of a low-power noise detection module using a conventional ADC for signal improvement. Taken together, the findings from this study demonstrate the potential use of switching activity information of an ADC to adaptively control the circuits, and simultaneously expanding the functionality of the ADC in electronic systems
êł ì ìëŠŹìŒ ë§íŹë„Œ ìí êł ëŠŹ ë°ì§êž°ë„Œ êž°ë°ìŒëĄ íë ìŁŒíì í©ì±êž°
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ŒëŹž(ë°ìŹ) -- ììžëíê”ëíì : êł”êłŒëí ì Ʞ·ì ëłŽêł”íë¶, 2022. 8. ì ëê· .In this dissertation, major concerns in the clocking of modern serial links are discussed. As sub-rate, multi-standard architectures are becoming predominant, the conventional clocking methodology seems to necessitate innovation in terms of low-cost implementation. Frequency synthesis with active, inductor-less oscillators replacing LC counterparts are reviewed, and solutions for two major drawbacks are proposed. Each solution is verified by prototype chip design, giving a possibility that the inductor-less oscillator may become a proper candidate for future high-speed serial links.
To mitigate the high flicker noise of a high-frequency ring oscillator (RO), a reference multiplication technique that effectively extends the bandwidth of the following all-digital phase-locked loop (ADPLL) is proposed. The technique avoids any jitter accumulation, generating a clean mid-frequency clock, overall achieving high jitter performance in conjunction with the ADPLL. Timing constraint for the proper reference multiplication is first analyzed to determine the calibration points that may correct the existent phase errors. The weight for each calibration point is updated by the proposed a priori probability-based least-mean-square (LMS) algorithm. To minimize the time required for the calibration, each gain for the weight update is adaptively varied by deducing a posteriori which error source dominates the others. The prototype chip is fabricated in a 40-nm CMOS technology, and its measurement results verify the low-jitter, high-frequency clock generation with fast calibration settling. The presented work achieves an rms jitter of 177/223 fs at 8/16-GHz output, consuming 12.1/17-mW power.
As the second embodiment, an RO-based ADPLL with an analog technique that addresses the high supply sensitivity of the RO is presented. Unlike prior arts, the circuit for the proposed technique does not extort the RO voltage headroom, allowing high-frequency oscillation. Further, the performance given from the technique is robust over process, voltage, and temperature (PVT) variations, avoiding the use of additional calibration hardware. Lastly, a comprehensive analysis of phase noise contribution is conducted for the overall ADPLL, followed by circuit optimizations, to retain the low-jitter output. Implemented in a 40-nm CMOS technology, the frequency synthesizer achieves an rms jitter of 289 fs at 8 GHz output without any injected supply noise. Under a 20-mVrms white supply noise, the ADPLL suppresses supply-noise-induced jitter by -23.8 dB.ëłž ë
ŒëŹžì íë ìëŠŹìŒ ë§íŹì íŽëœíčì êŽìŹëë ìŁŒìí 돞ì ë€ì ëíìŹ êž°ì íë€. ì€ìë, ë€ì€ íì€ ê”ŹìĄ°ë€ìŽ ì±íëêł ìë ì¶ìžì ë°ëŒ, êž°ìĄŽì íŽëŒíč ë°©ëČì ëźì ëčì©ì ê”Źíì êŽì ìì ìëĄìŽ íì ì íìëĄ íë€. LC êł”ì§êž°ë„Œ ëì íìŹ ë„ë ìì ë°ì§êž°ë„Œ ìŹì©í ìŁŒíì í©ì±ì ëíìŹ ììëłŽêł , ìŽì ë°ìíë ëê°ì§ ìŁŒì 돞ì ì êłŒ ê°ê°ì ëí íŽêČ° ë°©ìì íìíë€. ê° ì ì ë°©ëČì íëĄí íì
ìč©ì í”íŽ ê·ž íšì©ì±ì êČìŠíêł , ìŽìŽì ë„ë ìì ë°ì§êž°ê° 믞ëì êł ì ìëŠŹìŒ ë§íŹì íŽëœíčì ìŹì©ë ê°ë„ì±ì ëíŽ êČí íë€.
ìČ«ëČ짞 ìì°ìŒëĄìš, êł ìŁŒí êł ëŠŹ ë°ì§êž°ì ëì íëŠŹì»€ ìĄìì ìíìí€êž° ìíŽ êž°ì€ ì ížë„Œ ë°°ìííìŹ ë·ëšì ìì êł ì 룚íì ëìíì íšêłŒì ìŒëĄ ê·čëí ìí€ë íëĄ êž°ì ì ì ìíë€. ëłž êž°ì ì ì§í°ë„Œ ëì ìí€ì§ ììŒë©° ë°ëŒì êčšëí ì€ê° ìŁŒíì íŽëœì ìì±ììŒ ìì êł ì 룚íì íšê» ëì ì±ë„ì êł ìŁŒí íŽëœì í©ì±íë€. êž°ì€ ì ížë„Œ ì±êł”ì ìŒëĄ ë°°ìííêž° ìí íìŽë° ìĄ°ê±Žë€ì 뚌ì ë¶ìíìŹ íìŽë° ì€ë„ë„Œ ì ê±°íêž° ìí ë°©ëČëĄ ì íì
íë€. ê° ê”ì ì€ëì ì°ìì íë„ ì êž°ë°ìŒëĄí LMS ìêł ëŠŹìŠì í”íŽ ê°±ì ëëëĄ ì€êłëë€. ê”ì ì íìí ìê°ì ì”ìí íêž° ìíìŹ, ê° ê”ì ìŽëì íìŽë° ì€ë„ ê·Œìë€ì íŹêž°ë„Œ ê·ë©ì ìŒëĄ ì¶ëĄ í ê°ì ë°íìŒëĄ ì§ìì ìŒëĄ ì ìŽëë€. 40-nm CMOS êł”ì ìŒëĄ ê”Źíë íëĄí íì
ìč©ì ìžĄì ì í”íŽ ì ìì, êł ìŁŒí íŽëœì ëč ë„ž ê”ì ìê°ìì í©ì±íŽ ëì íìžíìë€. ìŽë 177/223 fsì rms ì§í°ë„Œ ê°ì§ë 8/16 GHzì íŽëœì ì¶ë „íë€.
ëëČ짞 ìì°ìŒëĄìš, êł ëŠŹ ë°ì§êž°ì ëì ì ì ë
žìŽìŠ ììĄŽì±ì ìíìí€ë êž°ì ìŽ íŹíšë ìŁŒíì í©ì±êž°ê° ì€êłëìë€. ìŽë êł ëŠŹ ë°ì§êž°ì ì ì í€ë룞ì ëłŽìĄŽíšìŒëĄì êł ìŁŒí ë°ì§ì ê°ë„íêČ íë€. ëìê°, ì ì ë
žìŽìŠ ê°ì ì±ë„ì êł”ì , ì ì, ìšë ëłëì ëíìŹ ëŻŒê°íì§ ììŒë©°, ë°ëŒì ì¶ê°ì ìž ê”ì íëĄë„Œ íìëĄ íì§ ìëë€. ë§ì§ë§ìŒëĄ, ìì ë
žìŽìŠì ëí íŹêŽì ë¶ìêłŒ íëĄ ì”ì íë„Œ í”íìŹ ìŁŒíì í©ì±êž°ì ì ìĄì ì¶ë „ì ë°©íŽíì§ ìë ë°©ëČì êł ìíìë€. íŽëč íëĄí íì
ìč©ì 40-nm CMOS êł”ì ìŒëĄ ê”ŹíëììŒë©°, ì ì ë
žìŽìŠê° ìžê°ëì§ ìì ìíìì 289 fsì rms ì§í°ë„Œ ê°ì§ë 8 GHzì íŽëœì ì¶ë „íë€. ëí, 20 mVrmsì ì ì ë
žìŽìŠê° ìžê°ëìì ëì ì ëëë ì§í°ì ìì -23.8 dB ë§íŒ ì€ìŽë êČì íìžíìë€.1 Introduction 1
1.1 Motivation 3
1.1.1 Clocking in High-Speed Serial Links 4
1.1.2 Multi-Phase, High-Frequency Clock Conversion 8
1.2 Dissertation Objectives 10
2 RO-Based High-Frequency Synthesis 12
2.1 Phase-Locked Loop Fundamentals 12
2.2 Toward All-Digital Regime 15
2.3 RO Design Challenges 21
2.3.1 Oscillator Phase Noise 21
2.3.2 Challenge 1: High Flicker Noise 23
2.3.3 Challenge 2: High Supply Noise Sensitivity 26
3 Filtering RO Noise 28
3.1 Introduction 28
3.2 Proposed Reference Octupler 34
3.2.1 Delay Constraint 34
3.2.2 Phase Error Calibration 38
3.2.3 Circuit Implementation 51
3.3 IL-ADPLL Implementation 55
3.4 Measurement Results 59
3.5 Summary 63
4 RO Supply Noise Compensation 69
4.1 Introduction 69
4.2 Proposed Analog Closed Loop for Supply Noise Compensation 72
4.2.1 Circuit Implementation 73
4.2.2 Frequency-Domain Analysis 76
4.2.3 Circuit Optimization 81
4.3 ADPLL Implementation 87
4.4 Measurement Results 90
4.5 Summary 98
5 Conclusions 99
A Notes on the 8REF 102
B Notes on the ACSC 105ë°
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Autonomously Reconfigurable Artificial Neural Network on a Chip
Artificial neural network (ANN), an established bio-inspired computing paradigm, has proved very effective in a variety of real-world problems and particularly useful for various emerging biomedical applications using specialized ANN hardware. Unfortunately, these ANN-based systems are increasingly vulnerable to both transient and permanent faults due to unrelenting advances in CMOS technology scaling, which sometimes can be catastrophic. The considerable resource and energy consumption and the lack of dynamic adaptability make conventional fault-tolerant techniques unsuitable for future portable medical solutions. Inspired by the self-healing and self-recovery mechanisms of human nervous system, this research seeks to address reliability issues of ANN-based hardware by proposing an Autonomously Reconfigurable Artificial Neural Network (ARANN) architectural framework. Leveraging the homogeneous structural characteristics of neural networks, ARANN is capable of adapting its structures and operations, both algorithmically and microarchitecturally, to react to unexpected neuron failures. Specifically, we propose three key techniques --- Distributed ANN, Decoupled Virtual-to-Physical Neuron Mapping, and Dual-Layer Synchronization --- to achieve cost-effective structural adaptation and ensure accurate system recovery. Moreover, an ARANN-enabled self-optimizing workflow is presented to adaptively explore a "Pareto-optimal" neural network structure for a given application, on the fly. Implemented and demonstrated on a Virtex-5 FPGA, ARANN can cover and adapt 93% chip area (neurons) with less than 1% chip overhead and O(n) reconfiguration latency. A detailed performance analysis has been completed based on various recovery scenarios
A 23ÎŒW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction
Voice-controlled interfaces on acoustic Internet-of-Things (IoT) sensor nodes and mobile devices require integrated low-power always-on wake-up functions such as Voice Activity Detection (VAD) and Keyword Spotting (KWS) to ensure longer battery life. Most VAD and KWS ICs focused on reducing the power of the feature extractor (FEx) as it is the most power-hungry building block. A serial Fast Fourier Transform (FFT)-based KWS chip [1] achieved 510nW; however, it suffered from a high 64ms latency and was limited to detection of only 1-to-4 keywords (2-to-5 classes). Although the analog FEx [2]â[3] for VAD/KWS reported 0.2ÎŒW-to-1 ÎŒW and 10ms-to-100ms latency, neither demonstrated >5 classes in keyword detection. In addition, their voltage-domain implementations cannot benefit from process scaling because the low supply voltage reduces signal swing; and the degradation of intrinsic gain forces transistors to have larger lengths and poor linearity
Recent Advances in Neural Recording Microsystems
The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons. These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications. They can extract the relevant control signals directly from the brain enabling individuals with severe disabilities to communicate their intentions to other devices, like computers or various prostheses. Such microsystems are self-contained devices composed of a neural probe attached with an integrated circuit for extracting neural signals from multiple channels, and transferring the data outside the body. The greatest challenge facing development of such emerging devices into viable clinical systems involves addressing their small form factor and low-power consumption constraints, while providing superior resolution. In this paper, we survey the recent progress in the design and the implementation of multi-channel neural recording Microsystems, with particular emphasis on the design of recording and telemetry electronics. An overview of the numerous neural signal modalities is given and the existing microsystem topologies are covered. We present energy-efficient sensory circuits to retrieve weak signals from neural probes and we compare them. We cover data management and smart power scheduling approaches, and we review advances in low-power telemetry. Finally, we conclude by summarizing the remaining challenges and by highlighting the emerging trends in the field
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