4,092 research outputs found

    Ring oscillator clocks and margins

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    How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.Peer ReviewedPostprint (author's final draft

    Impact of parameter variations on circuits and microarchitecture

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    Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits. This article presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches.Peer ReviewedPostprint (published version

    Adaptive Latency Insensitive Protocols

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    Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail

    Specification and validation of control intensive ICs in hopCP

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    technical reportControl intensive ICs pose a significant challenge to the users of formal methods in designing hardware. These ICs have to support a wide variety of requirements including synchronous and asynchronous operations polling and interrupt driven modes of operation multiple concurrent threads of execution non-trivial computational requirements and programmability. In this paper we illustrate the use of formal methods in the design of a control intensive IC called the "Intel 8251" Universal Synchronous / Asynchronous Receiver Transmitter (USART), using our hardware description language 'hopCP'. A feature of hopCP is that it supports communication via synchronous ports in addition to synchronous message passing Asynchronous ports are distributed shared variables writable by exactly one process We show the usefulness of this combination of communication constructs We outline algorithms to determine safe usages of asynchronous ports and also to discover other static properties of the specification We discuss a compiled code concurrent functional simulator called CFSIM, as well as the use of concurrent testers for driving CFSIM. The use of a semantically well specified and simple language and the associated analysis/simulation tools helps conquer the complexity of specifying and validating control intensive ICs

    CAD Tools for Synthesis of Sleep Convention Logic

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    This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design

    Modular Timing Constraints for Delay-Insensitive Systems

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    This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component’s gate-level circuit implementation obeys the component’s handshake protocol specification. Because the handshake protocols are delayinsensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis (STA) code to validate and enforce the component’s constraints in any self-timed system built using the library. The library descriptions of a handshake component’s circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works

    Simulating Building Blocks for Spikes Signals Processing

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    In this paper we will explain in depth how we have used Simulink with the addition of Xilinx System Generation to design a simulation framework for testing and analyzing neuro-inspired elements for spikes rate coded signals processing. Those elements have been designed as building blocks, which represent spikes processing primitives, combining them we have designed more complex blocks, which behaves like analog frequency filter using digital circuits. This kind of computation performs a massively parallel processing without complex hardware units. Spikes processing building blocks have been written in VHDL to be implemented for FPGA. Xilinx System Generator allows co-simulating VHDL entities together with Simulink components, providing an easy interface for presented building block simulations and analysis.Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

    Formally-Based Design Evaluation (extended version)

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    This paper investigates specification, verification and test generation for synchronous and asynchronous circuits. The approach is called DILL (Digital Logic in LOTOS). DILL models are discussed for synchronous and asynchronous circuits. Relations for (strong) conformance are defined for verifying a design specification against a high-level specification. An algorithm is also outlined for generating and applying implementation tests based on a specification. Tools have been developed for automated test generation and verification of conformance between an implementation and its specification. The approach is illustrated with various benchmark circuits as case studies
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