639 research outputs found

    Contactless Test Access Mechanism for 3D IC

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    3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

    An asynchronous java processor for smart card.

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    Yu Chun-Pong.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 60-61).Abstracts in English and Chinese.Abstract of this thesis entitled: --- p.i摘要 --- p.iiiAcknowledgements --- p.ivTable of contents --- p.vList of Tables --- p.viList of Figures --- p.viiChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Asynchronous design --- p.1Chapter 1.2 --- Java processor for contactless smart card [3] --- p.2Chapter 1.3 --- Motivation --- p.3Chapter Chapter 2 --- Asynchronous circuit design techniques --- p.5Chapter 2.1 --- Overview --- p.5Chapter 2.2 --- Handshake protocol --- p.5Chapter 2.3 --- Asynchronous pipeline --- p.7Chapter 2.4 --- Asynchronous control elements --- p.9Chapter Chapter 3 --- Asynchronous Java Processor --- p.15Chapter 3.1 --- Instruction Set --- p.15Chapter 3.2 --- Architecture of the java processor --- p.17Chapter 3.3 --- Basic building blocks of the java processor --- p.22Chapter 3.4 --- Token flow --- p.32Chapter Chapter 4 --- Results and Discussion --- p.37Chapter 4.1 --- Simulation Results of test programs --- p.37Chapter 4.2 --- Experimental result --- p.41Chapter 4.3 --- Future work --- p.42Chapter Chapter 5 --- Conclusion --- p.45Appendix --- p.47Chip micrograph for the java processor core --- p.47Pin assignment of the java processor --- p.48Schematic of the java processor --- p.52Schematic of the decoder --- p.54Schematic of the Stage2 of the java processor --- p.55Schematic of the stack --- p.56Schematic of the block of the local variables --- p.57Schematic of the 16-bit self-timed adder --- p.58The schematic and the layout of the memory cell --- p.59Reference --- p.6

    Workshops at IMS2023

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    Lists future events that should be of interest to practitioners and researchers.Peer ReviewedPostprint (published version

    A DLL Based Test Solution for 3D ICs

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    Integrated circuits (ICs) are rapidly changing and vertical integration and packaging strategies have already become an important research topic. 2.5D and 3D IC integrations have obvious advantages over the conventional two dimensional IC implementations in performance, capacity, and power consumption. A passive Si interposer utilizing Through-Silicon via (TSV) technology is used for 2.5D IC integration. TSV is also the enabling technology for 3D IC integration. TSV manufacturing defects can affect the performance of stacked devices and reduce the yield. Manufacturing test methodologies for TSVs have to be developed to ensure fault-free devices. This thesis presents two test methods for TSVs in 2.5D and 3D ICs utilizing Delay-Locked Loop (DLL) modules. In the test method developed for TSVs in 2.5D ICs, a DLL is used to determine the propagation delay for fault detection. TSV faults in 3D ICs are detected through observation of the control voltage of a DLL. The proposed test methods present a robust performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLLs. 3D full-wave simulations are performed to extract circuit level models for TSVs and fragments of an interposer wires using HFSS simulation tools. The extracted TSV models are then used to perform circuit level simulations using ADS tools from Agilent. Simulation results indicate that the proposed test solution for TSVs can detect manufacturing defects affecting the TSV propagation delay

    TSV Equivalent Circuit Model using 3D Full-Wave Analysis

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    This work presents a study to build lumped models for fault-free and faulty Through Silicon Vias (TSVs). Three dimensional full-wave simulations are performed to extract equivalent circuit models. The effects of parametric and catastrophic faults due to pin-holes, voids and open circuits on the equivalent circuit models have been determined through 3D simulations. The extracted TSV models are then used to conduct delay tests to determine the required measurement resolution to detect TSV defects. It is shown that the substrate conductivity has a considerable effect on TSV fault characterization. It is also shown that, regardless of the substrate type, even a relatively large void does not alter the TSV resistance or its parasitic capacitance noticeably at 1GHz solution frequency. An on-chip test solution for TSV parametric faults requires a dedicated high resolution measurement circuit due to the minor variations of TSV circuit model parameters

    An On-chip PVT Resilient Short Time Measurement Technique

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    As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans

    Signaling in 3-D integrated circuits, benefits and challenges

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    Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

    RFID Logic circuit with oxide TFTs modeled by genetic algorithms

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    Nos últimos anos, a necessidade por técnicas de identificação com velocidades de leitura superiores e maior flexibilidade relativamente à memória e programabilidade, levaram ao desenvolvimento de tecnologias de identificação de rádio frequência (RFID). Esta tecnologia já provou o seu valor no futuro da Internet das coisas (IoT), ao permitir a possibilidade de marcar qualquer tipo de produto facilmente e com baixo custo por etiqueta, enquanto possibilita a conexão deste tipo de etiquetas com smartphones para aumentar a ligação entre os dispositivos RFID e a vida quotidiana. Além disto, a introdução de transístores de filme fino (TFT) de óxidos amorfos em circuitos RFID, abre um novo mundo de aplicações, visto que este tipo de dispositivos permite o uso de substratos transparentes e/ou flexíveis, devido à possibilidade de usar baixas temperaturas durante o processo de fabrico para este tipo de transístores. Neste trabalho, foi usado o Modelo a-Si Nível 61 com a ajuda de algoritmos genéticos para criar modelos de transístores de a-IGZO produzidos com um dielétrico de porta depositado por métodos de solução usando spin-coating. Com estes modelos, foi dimensionado um circuito digital de RFID, usando uma topologia em que o transístor de carga está em configuração de díodo, para ler uma memória ROM de 16-bit e posteriormente codificar o sinal através de uma codificação de Manchester com uma taxa de transferência de 14 kbit/s. Este tipo de circuitos utilizando substratos transparentes e/ou flexíveis pode possibilitar no futuro a criação de embalagens inteligentes para bens domésticos e a posterior integração numa configuração de frigoríficos inteligentes. Isto significa que poderá ser possível uma pessoa ser avisada quando é necessário comprar um produto ou quando ultrapassa o prazo de validade.In recent years, the need for identification techniques, with faster reading speed and more flexibility regarding memory and programmability, led to the development of Radio Frequency Identification technologies. This technology has already proven to be essential in the future of Internet-of-Things, by allowing the possibility of tagging any type of product easily and at low cost per tag, while also allowing the interface of these tags, with common smartphones to increase the connectivity of RFID devices in daily life. Furthermore, the introduction of amorphous IGZO thin film transistors in RFID circuits, opens a new world of applications since this type of devices allows the use of transparent and/or flexible substrates, due to the low temperatures required during the fabrication process. In this work, it was used the a-Si Level 61 TFT Model together with genetic algorithms, to model a-IGZO transistors produced, with a gate dielectric deposited by a solution method using spin coating. With these models, it was designed an RFID logic circuit, which employs diode connected structures, to read a 16-bit Read Only Memory and encode the signal using a Manchester encoding technique, with a data rate of 14 kbit/s. These types of circuits using transparent and/or flexible substrates could allow, in the future, the creation of smart packaging for regular house goods and integrate it in a smart fridge configuration. Meaning that, it could be possible to a person either to be advised when to buy a certain item or when it reaches the expiration date

    Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

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    The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system
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