Many-core and heterogeneous architectures: programming models and compilation toolchains

1noL'abstract è presente nell'allegato / the abstract is in the attachmentopen677. INGEGNERIA INFORMATInopartially_openembargoed_20211002Barchi, Francesc

CROSS-LAYER DESIGN, OPTIMIZATION AND PROTOTYPING OF NoCs FOR THE NEXT GENERATION OF HOMOGENEOUS MANY-CORE SYSTEMS

This thesis provides a whole set of design methods to enable and manage the runtime heterogeneity of features-rich industry-ready Tile-Based Networkon- Chips at different abstraction layers (Architecture Design, Network Assembling, Testing of NoC, Runtime Operation). The key idea is to maintain the functionalities of the original layers, and to improve the performance of architectures by allowing, joint optimization and layer coordinations. In general purpose systems, we address the microarchitectural challenges by codesigning and co-optimizing feature-rich architectures. In application-specific NoCs, we emphasize the event notification, so that the platform is continuously under control. At the network assembly level, this thesis proposes a Hold Time Robustness technique, to tackle the hold time issue in synchronous NoCs. At the network architectural level, the choice of a suitable synchronization paradigm requires a boost of synthesis flow as well as the coexistence with the DVFS. On one hand this implies the coexistence of mesochronous synchronizers in the network with dual-clock FIFOs at network boundaries. On the other hand, dual-clock FIFOs may be placed across inter-switch links hence removing the need for mesochronous synchronizers. This thesis will study the implications of the above approaches both on the design flow and on the performance and power quality metrics of the network. Once the manycore system is composed together, the issue of testing it arises. This thesis takes on this challenge and engineers various testing infrastructures. At the upper abstraction layer, the thesis addresses the issue of managing the fully operational system and proposes a congestion management technique named HACS. Moreover, some of the ideas of this thesis will undergo an FPGA prototyping. Finally, we provide some features for emerging technology by characterizing the power consumption of Optical NoC Interfaces

Runtime Hardware Reconfiguration in Wireless Sensor Networks for Condition Monitoring

The integration of miniaturized heterogeneous electronic components has enabled the deployment of tiny sensing platforms empowered by wireless connectivity known as wireless sensor networks. Thanks to an optimized duty-cycled activity, the energy consumption of these battery-powered devices can be reduced to a level where several years of operation is possible. However, the processing capability of currently available wireless sensor nodes does not scale well with the observation of phenomena requiring a high sampling resolution. The large amount of data generated by the sensors cannot be handled efficiently by low-power wireless communication protocols without a preliminary filtering of the information relevant for the application. For this purpose, energy-efficient, flexible, fast and accurate processing units are required to extract important features from the sensor data and relieve the operating system from computationally demanding tasks. Reconfigurable hardware is identified as a suitable technology to fulfill these requirements, balancing implementation flexibility with performance and energy-efficiency. While both static and dynamic power consumption of field programmable gate arrays has often been pointed out as prohibitive for very-low-power applications, recent programmable logic chips based on non-volatile memory appear as a potential solution overcoming this constraint. This thesis first verifies this assumption with the help of a modular sensor node built around a field programmable gate array based on Flash technology. Short and autonomous duty-cycled operation combined with hardware acceleration efficiently drop the energy consumption of the device in the considered context. However, Flash-based devices suffer from restrictions such as long configuration times and limited resources, which reduce their suitability for complex processing tasks. A template of a dynamically reconfigurable architecture built around coarse-grained reconfigurable function units is proposed in a second part of this work to overcome these issues. The module is conceived as an overlay of the sensor node FPGA increasing the implementation flexibility and introducing a standardized programming model. Mechanisms for virtual reconfiguration tailored for resource-constrained systems are introduced to minimize the overhead induced by this genericity. The definition of this template architecture leaves room for design space exploration and application- specific customization. Nevertheless, this aspect must be supported by appropriate design tools which facilitate and automate the generation of low-level design files. For this purpose, a software tool is introduced to graphically configure the architecture and operation of the hardware accelerator. A middleware service is further integrated into the wireless sensor network operating system to bridge the gap between the hardware and the design tools, enabling remote reprogramming and scheduling of the hardware functionality at runtime. At last, this hardware and software toolchain is applied to real-world wireless sensor network deployments in the domain of condition monitoring. This category of applications often require the complex analysis of signals in the considered range of sampling frequencies such as vibrations or electrical currents, making the proposed system ideally suited for the implementation. The flexibility of the approach is demonstrated by taking examples with heterogeneous algorithmic specifications. Different data processing tasks executed by the sensor node hardware accelerator are modified at runtime according to application requests

Ein modulares Konzept von Klassifikatoren für Aktivitätserkennung auf Mobiltelefonen

In this thesis a modular activity recognition using accelerometer sensors on mobile phones is presented, which includes solutions to five challenges: 1.Flexibility: The conditions of the mobile phone usage and therefore for the activity recognition can always change. An activity recognition needs to flexibly adapt to this changes. 2.Extensibility: Different users have different demands of activities to be recognized. Only a small set of activities are performed by nearly every user. Therefore, the recognition needs to be extensible to the individual needs. 3.Robustness: The device is typically not firmly attached to any position, which results in noisy sensor data. A robust recognition is needed, which is able to detect the activities with high accuracy. 4.Resources: The resources on mobile phones are limited (processor and battery capacity), therrfore the activity recognition needs not to have a high impact on these. 5.Conditionality: The user and her phone can be situated in various different conditions. Each of these conditionalities implies different sensor patterns, which need representation in the activity recognition algorithm. The modularity of the proposed approach enables the individual adaption of parts of the activity recognition to offer flexibility. A modular recognition is extensible by new modules which detect new activities. The recurrence of the classification process stabilizes the recognition and enables the derivation of a reliability measure. Only one module and not the whole activity recognition is active at each point in time, which decreases the calculation effort and therefore the energy consumption. Each module can be suited for dealing with one conditionality, through which neither the complexity of the recognition is increased nor the accuracy is significantly lowered. All these solutions to the challenges of activity recognition on mobile phones are rounded by a service, which supports the novel system on the common user's phone.In dieser Dissertation wird eine modulare Aktivitätserkennung mit Beschleunigungssensoren auf Mobiltelefonen vorgestellt, die Lösungen für folgende fünf Herausforderungen bereitstellt: 1.Flexibilität: Die Bedingungen der Nutzung eines Mobiltelefons und damit auch für die Aktivitätserkennung können sich jederzeit ändern. Eine Aktivitätserkennung muss flexibel auf diese Veränderungen reagieren können. 2.Erweiterbarkeit: Unterschiedliche Anwender haben unterschiedliche Anforderungen welche Aktivitäten erkannt werden sollen. Daher muss die Erkennung erweiterbar sein, um die individuellen Bedürfnisse befriedigen zu können. 3.Robustheit: Das Gerät ist typischerweise nicht fest an einer Position angebracht, woraus verrauschten Sensordaten resultieren. Desswegen ist eine robuste Erkennung erforderlich, welche in der Lage ist die Aktivitäten trotzdem mit hoher Genauigkeit zu detektieren. 4.Resources: Die Ressourcen (Prozessor und Akku-Kapazität) auf Handys sind beschränkt, weshalb die Aktivitätserkennung diese nicht noch zusätzlich übermäßig einschränken sollte. 5.Konditionalität: Der Benutzer und sein Telefon können in verschiedensten Gegebenheiten situiert sein. Jede dieser Konditionen impliziert andere Muster der Sensoren, welche jeweils durch die Aktivitätserkennung repräsentiert sein müssen. Durch die Modularität, welche in dieser Dissertation zur Bewältigung der Herausforderungen vorgeschlagen wird, wird ermöglicht, dass Flexibilität bereitgestellt werden kann. Eine modulare Erkennung ist erweiterbar durch neue Module, welche neue Aktivitäten erkennen. Die Rekurrenz des Klassifikationsprozesses stabilisiert die Erkennung. Nur ein Modul ist zu einem Zeitpunkt aktiv, was Ressourcen schont. Jedes Modul kann passend sein, um mit einer Konditionalität umzugehen, wobei die Komplexität weder erheblich erhöht noch die Genauigkeit stark erniedrigt wird. Alle diese Lösungen für die Herausforderungen der Aktivitätserkennung werden durch einen speziellen Service abgerundet