3,034 research outputs found
One-by-one trap activation in silicon nanowire transistors
Flicker or 1/f noise in metal-oxide-semiconductor field-effect transistors
(MOSFETs) has been identified as the main source of noise at low frequency. It
often originates from an ensemble of a huge number of charges trapping and
detrapping. However, a deviation from the well-known model of 1/f noise is
observed for nanoscale MOSFETs and a new model is required. Here, we report the
observation of one-by-one trap activation controlled by the gate voltage in a
nanowire MOSFET and we propose a new low-frequency-noise theory for nanoscale
FETs. We demonstrate that the Coulomb repulsion between electronically charged
trap sites avoids the activation of several traps simultaneously. This effect
induces a noise reduction by more than one order of magnitude. It decreases
when increasing the electron density in the channel due to the electrical
screening of traps. These findings are technologically useful for any FETs with
a short and narrow channel.Comment: One file with paper and supplementary informatio
Nanowire Zinc Oxide MOSFET Pressure Sensor
Fabrication and characterization of a new kind of pressure sensor using self-assembly Zinc Oxide (ZnO) nanowires on top of the gate of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Self-assembly ZnO nanowires were fabricated with a diameter of 80 nm and 800 nm height (80:8 aspect ratio) on top of the gate of the MOSFET. The sensor showed a 110% response in the drain current due to pressure, even with the expected piezoresistive response of the silicon device removed from the measurement. The pressure sensor was fabricated through low temperature bottom up ultrahigh aspect ratio ZnO nanowire growth using anodic alumina oxide (AAO) templates. The pressure sensor has two main components: MOSFET and ZnO nanowires. Silicon Dioxide growth, photolithography, dopant diffusion, and aluminum metallization were used to fabricate a basic MOSFET. In the other hand, a combination of aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and wet etching for nanowire release were optimized to fabricate the sensor on a silicon wafer. The ZnO nanowire fabrication sequence presented is at low temperature making it compatible with CMOS technology
Dispersively detected Pauli Spin-Blockade in a Silicon Nanowire Field-Effect Transistor
We report the dispersive readout of the spin state of a double quantum dot
formed at the corner states of a silicon nanowire field-effect transistor. Two
face-to-face top-gate electrodes allow us to independently tune the charge
occupation of the quantum dot system down to the few-electron limit. We measure
the charge stability of the double quantum dot in DC transport as well as
dispersively via in-situ gate-based radio frequency reflectometry, where one
top-gate electrode is connected to a resonator. The latter removes the need for
external charge sensors in quantum computing architectures and provides a
compact way to readout the dispersive shift caused by changes in the quantum
capacitance during interdot charge transitions. Here, we observe Pauli
spin-blockade in the high-frequency response of the circuit at finite magnetic
fields between singlet and triplet states. The blockade is lifted at higher
magnetic fields when intra-dot triplet states become the ground state
configuration. A lineshape analysis of the dispersive phase shift reveals
furthermore an intradot valley-orbit splitting of 145 eV.
Our results open up the possibility to operate compact CMOS technology as a
singlet-triplet qubit and make split-gate silicon nanowire architectures an
ideal candidate for the study of spin dynamics
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