74,033 research outputs found

    Timing the Information System Upgrade

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    A system upgrade requires careful planning as its implications to organizational systems might beenormous. Although in IS literature the requirements and process of systems upgrade have been discussed,the timing when to upgrade and what factors guide it has been of lesser interest. Consequently,in this paper we focus on information systems upgrading and its timing from the perspectiveof the user organization. Upgrading is enabled by the availability of a new software version. When toupgrade, meanwhile, is determined by the business interests of the customer organization, businesscalendar, development projects, and the vendor. These factors were identified by interviewing 14 ITmanagers, mainly CIOs, from middle size to large organizations in Finland. They presented 16 differentcases of upgrading or modifications of enterprise systems or similar undertakings. The analysis ofthe cases and the identification of the upgrade timing factors not only increase our understanding ofthe phenomena in general, but also reveal the customer’s motives and interests regarding IS upgradingand its timing

    A new readout control system for the LHCb upgrade at CERN

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    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and a first hardware implementation of a new fast Readout Control system for the LHCb upgrade, which will be entirely based on FPGAs and bi-directional links. We also outline the real-time implementations of the new Readout Control system, together with solutions on how to handle the synchronous distribution of timing and synchronous information to the complex upgraded LHCb readout architecture. One section will also be dedicated to the control and usage of the newly developed CERN GBT chipset to transmit fast and slow control commands to the upgraded LHCb Front-End electronics. At the end, we outline the plans for the deployment of the system in the global LHCb upgrade readout architecture

    Optimization on fixed low latency implementation of GBT protocol in FPGA

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    In the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper

    Status of the TTC upgrade

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    The TTC (Timing, Trigger and Control) system [1] broadcasts the timing signals (Bunch Clocks and Orbits) from the LHC machine to the experiments. Once at the detector level, it integrates the trigger information and local synchronous commands with these signals, for transmission to several thousands of destinations. The equipment for this second part of the system is fully produced, but the main network between the machine and the experiments required to be upgraded to ensure its easy maintenance. The design work began at the end of 2005 and the new modules will be tested during the summer 2006 and the structured test beam in September 2006. A status of this design work is given, including the description of the upgrade principle, the main modules, the results of the tests done on the prototypes and the plans for production and support of this system

    Test beam results of the GE1/1 prototype for a future upgrade of the CMS high-η\eta muon system

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    Gas Electron Multipliers (GEM) are an interesting technology under consideration for the future upgrade of the forward region of the CMS muon system, specifically in the 1.6<η<2.41.6<| \eta |<2.4 endcap region. With a sufficiently fine segmentation GEMs can provide precision tracking as well as fast trigger information. The main objective is to contribute to the improvement of the CMS muon trigger. The construction of large-area GEM detectors is challenging both from the technological and production aspects. In view of the CMS upgrade we have designed and built the largest full-size Triple-GEM muon detector, which is able to meet the stringent requirements given the hostile environment at the high-luminosity LHC. Measurements were performed during several test beam campaigns at the CERN SPS in 2010 and 2011. The main issues under study are efficiency, spatial resolution and timing performance with different inter-electrode gap configurations and gas mixtures. In this paper results of the performance of the prototypes at the beam tests will be discussed

    The upgrade of the LHCb trigger system

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    The LHCb experiment will operate at a luminosity of 2×10332\times10^{33} cm2^{-2}s1^{-1} during LHC Run 3. At this rate the present readout and hardware Level-0 trigger become a limitation, especially for fully hadronic final states. In order to maintain a high signal efficiency the upgraded LHCb detector will deploy two novel concepts: a triggerless readout and a full software trigger.Comment: Proceedings of the Workshop on Intelligent Trackers, 14-16 May 2014, University of Pennsylvani

    The RPC-based proposal for the ATLAS forward muon trigger upgrade in view of super-LHC

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    The innermost station of the present ATLAS forward muon detector needs to be upgraded for the super-LHC. We present a proposal to replace it with a sandwiched detector composed of several layers of small-radius Monitored Drift Tube chambers (sMDT) for precision tracking measurement and two stations of multi-gap Resistive Plate Chambers (mRPC) for triggering purpose. We describe the layout of the upgraded detector and the trigger strategy. Several modifications to the RPCs used in the ATLAS barrel region are needed to satisfy the super-LHC requirements. Various studies with the proposed mRPC timing resolution, spatial resolution and rate capability have been performed.Comment: 6 pages, 8 figures, proceeding for XI workshop on Resistive Plate Chambers and Related Detectors - RCP201
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