Design and implementation of a downlink MC-CDMA receiver

Cette thèse présente une étude d'un système complet de transmission en liaison descendante utilisant la technologie multi-porteuse avec l'accès multiple par division de code (Multi-Carrier Code Division Multiple Access, MC-CDMA). L'étude inclut la synchronisation et l'estimation du canal pour un système MC-CDMA en liaison descendante ainsi que l'implémentation sur puce FPGA d'un récepteur MC-CDMA en liaison descendante en bande de base. Le MC-CDMA est une combinaison de la technique de multiplexage par fréquence orthogonale (Orthogonal Frequency Division Multiplexing, OFDM) et de l'accès multiple par répartition de code (CDMA), et ce dans le but d'intégrer les deux technologies. Le système MC-CDMA est conçu pour fonctionner à l'intérieur de la contrainte d'une bande de fréquence de 5 MHz pour les modèles de canaux intérieur/extérieur pédestre et véhiculaire tel que décrit par le "Third Genaration Partnership Project" (3GPP). La composante OFDM du système MC-CDMA a été simulée en utilisant le logiciel MATLAB dans le but d'obtenir des paramètres de base. Des codes orthogonaux à facteur d'étalement variable (OVSF) de longueur 8 ont été choisis comme codes d'étalement pour notre système MC-CDMA. Ceci permet de supporter des taux de transmission maximum jusquà 20.6 Mbps et 22.875 Mbps (données non codées, pleine charge de 8 utilisateurs) pour les canaux intérieur/extérieur pédestre et véhiculaire, respectivement. Une étude analytique des expressions de taux d'erreur binaire pour le MC-CDMA dans un canal multivoies de Rayleigh a été réalisée dans le but d'évaluer rapidement et de façon précise les performances. Des techniques d'estimation de canal basées sur les décisions antérieures ont été étudiées afin d'améliorer encore plus les performances de taux d'erreur binaire du système MC-CDMA en liaison descendante. L'estimateur de canal basé sur les décisions antérieures et utilisant le critère de l'erreur quadratique minimale linéaire avec une matrice' de corrélation du canal de taille 64 x 64 a été choisi comme étant un bon compromis entre la performance et la complexité pour une implementation sur puce FPGA. Une nouvelle séquence d'apprentissage a été conçue pour le récepteur dans la configuration intérieur/extérieur pédestre dans le but d'estimer de façon grossière le temps de synchronisation et le décalage fréquentiel fractionnaire de la porteuse dans le domaine du temps. Les estimations fines du temps de synchronisation et du décalage fréquentiel de la porteuse ont été effectués dans le domaine des fréquences à l'aide de sous-porteuses pilotes. Un récepteur en liaison descendante MC-CDMA complet pour le canal intérieur /extérieur pédestre avec les synchronisations en temps et en fréquence en boucle fermée a été simulé avant de procéder à l'implémentation matérielle. Le récepteur en liaison descendante en bande de base pour le canal intérieur/extérieur pédestre a été implémenté sur un système de développement fabriqué par la compagnie Nallatech et utilisant le circuit XtremeDSP de Xilinx. Un transmetteur compatible avec le système de réception a également été réalisé. Des tests fonctionnels du récepteur ont été effectués dans un environnement sans fil statique de laboratoire. Un environnement de test plus dynamique, incluant la mobilité du transmetteur, du récepteur ou des éléments dispersifs, aurait été souhaitable, mais n'a pu être réalisé étant donné les difficultés logistiques inhérentes. Les taux d'erreur binaire mesurés avec différents nombres d'usagers actifs et différentes modulations sont proches des simulations sur ordinateurs pour un canal avec bruit blanc gaussien additif

Bit Loading and Peak Average Power Reduction Techniques for Adaptive Orthogonal Frequency Division Multiplexing Systems

In a frequency-selective channel a large number of resolvable multipaths are present which lead to the fading of the signal. Orthogonal frequency division multiplexing (OFDM) is well-known to be effective against multipath distortion. It is a multicarrier communication scheme, in which the bandwidth of the channel is divided into subcarriers and data symbols are modulated and transmitted on each subcarrier simultaneously. By inserting guard time that is longer than the delay spread of the channel, an OFDM system is able to mitigate intersymbol interference (ISI). Significant improvement in performance is achieved by adaptively loading the bits on the subcarriers based on the channel state information from the receiver. Imperfect channel state information (CSI) arises from noise at the receiver and also due to the time delay in providing the information to the transmitter for the next data transmission. This thesis presents an investigation into the different adaptive techniques for loading the data bits on the subcarriers. The choice of the loading technique is application specific. The spectral efficiency and the bit error rate (BER) performance of adaptive OFDM as well as the implementation complexity of the different loading algorithms is studied by varying any one of the parameters, data rate or BER or total transmit power subject to the constraints on the other two. A novel bit loading algorithm based on comparing the SNR with the threshold in order to minimize the BER is proposed and its performance for different data rates is plotted. Finally, this thesis presents a method for reducing the large peak to average power ratio (PAPR) problem with OFDM which arises when the sinusoidal signals of the subcarriers add constructively. The clipping and the probabilistic approaches were studied. The probabilistic technique shows comparatively better BER performance as well as reduced PAPR ratio but is more complex to implement

A Novel SNR Estimation Technique for OFDM Systems

Orthogonal Frequency Division Multiplexing (OFDM) systems have received a lot of attention because of their robust performance in frequency dispersive channels. Further performance improvement is achieved by employing more sophisticated receiver techniques that often require the knowledge of signal-to-noise ratio (SNR) - broadly defined as the ratio of the desired signal power to the unwanted noise power. For example, noise variance and, hence, signal to noise ratio (SNR) estimates of the received signal are very important for the channel quality control in communication systems. Similarly, in advanced communication systems, SNR estimation is used for adaptive algorithms for modulation, power control and coding. The objective of the work undertaken in this thesis is to design a front-end noise power estimator and, thence, SNR estimator. The proposed SNR estimator utilizes the OFDM preamble signal - the preamble used for synchronization. The estimation is achieved by auto correlating the preamble and it is deployed right at the front-end of the receiver. Noise power and, hence, signal power is estimated from the correlation results. The technique is also extended to obtaining noise power estimates of colored noise using wavelet-packet based filter bank analysis of the noise. In order to benchmark the proposed noise power and SNR estimation technique, a complete end-to-end fixed-broadband-wireless-access-system (IEEE 802.16d) simulation has been developed and the results are compared with other works reported in the literature. The simulations are conducted in both frequency non-dispersive and dispersive channels with real additive white Gaussian noise (A WGN) and also colored noise. It is observed that the proposed estimator gives better SNR estimates. The proposed estimator is also checked with WiMAX systems (IEEE802.\6d, 2004) using SUI multipath channels and with Wi-Fi systems (IEEE802.11 a) with indoor channel models. The estimator performs SNR estimation at front-end of the receiver unlike all other estimators which perform SNR estimation at back-end of the receiver. Furthermore, the proposed estimator has relatively low computational complexity; for it makes use of only one OFDM preamble signal to find the SNR estimates. The criteria of good SNR estimator are accuracy of estimates, low complexity and easy to implement. The results show that the proposed estimator fulfills these criteria successfully

Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases

[EN] The first generation of Terrestrial Digital Television(DTV) has been in service for over a decade. In 2013, several countries have already completed the transition from Analog to Digital TV Broadcasting, most of which in Europe. In South America, after several studies and trials, Brazil adopted the Japanese standard with some innovations. Japan and Brazil started Digital Terrestrial Television Broadcasting (DTTB) services in December 2003 and December 2007 respectively, using Integrated Services Digital Broadcasting - Terrestrial (ISDB-T), also known as ARIB STD-B31. In June 2005 the Committee for the Information Technology Area (CATI) of Brazilian Ministry of Science and Technology and Innovation MCTI approved the incorporation of the IC-Brazil Program, in the National Program for Microelectronics (PNM) . The main goals of IC-Brazil are the formal qualification of IC designers, support to the creation of semiconductors companies focused on projects of ICs within Brazil, and the attraction of semiconductors companies focused on the design and development of ICs in Brazil. The work presented in this thesis originated from the unique momentum created by the combination of the birth of Digital Television in Brazil and the creation of the IC-Brazil Program by the Brazilian government. Without this combination it would not have been possible to make these kind of projects in Brazil. These projects have been a long and costly journey, albeit scientifically and technologically worthy, towards a Brazilian DTV state-of-the-art low complexity Integrated Circuit, with good economy scale perspectives, due to the fact that at the beginning of this project ISDB-T standard was not adopted by several countries like DVB-T. During the development of the ISDB-T receiver proposed in this thesis, it was realized that due to the continental dimensions of Brazil, the DTTB would not be enough to cover the entire country with open DTV signal, specially for the case of remote localizations far from the high urban density regions. Then, Eldorado Research Institute and Idea! Electronic Systems, foresaw that, in a near future, there would be an open distribution system for high definition DTV over satellite, in Brazil. Based on that, it was decided by Eldorado Research Institute, that would be necessary to create a new ASIC for broadcast satellite reception. At that time DVB-S2 standard was the strongest candidate for that, and this assumption still stands nowadays. Therefore, it was decided to apply to a new round of resources funding from the MCTI - that was granted - in order to start the new project. This thesis discusses in details the Architecture and Algorithms proposed for the implementation of a low complexity Intermediate Frequency(IF) ISDB-T Receiver on Application Specific Integrated Circuit (ASIC) CMOS. The Architecture proposed here is highly based on the COordinate Rotation Digital Computer (CORDIC) Algorithm, that is a simple and efficient algorithm suitable for VLSI implementations. The receiver copes with the impairments inherent to wireless channels transmission and the receiver crystals. The thesis also discusses the Methodology adopted and presents the implementation results. The receiver performance is presented and compared to those obtained by means of simulations. Furthermore, the thesis also presents the Architecture and Algorithms for a DVB-S2 receiver targeting its ASIC implementation. However, unlike the ISDB-T receiver, only preliminary ASIC implementation results are introduced. This was mainly done in order to have an early estimation of die area to prove that the project in ASIC is economically viable, as well as to verify possible bugs in early stage. As in the case of ISDB-T receiver, this receiver is highly based on CORDIC algorithm and it was prototyped in FPGA. The Methodology used for the second receiver is derived from that used for the ISDB-T receiver, with minor additions given the project characteristics.[ES] La primera generación de Televisión Digital Terrestre(DTV) ha estado en servicio por más de una década. En 2013, varios países completaron la transición de transmisión analógica a televisión digital, la mayoría de ellas en Europa. En América del Sur, después de varios estudios y ensayos, Brasil adoptó el estándar japonés con algunas innovaciones. Japón y Brasil comenzaron a prestar el servicio de Difusión de Televisión Digital Terrestre (DTTB) en diciembre de 2003 y diciembre de 2007 respectivamente, utilizando Radiodifusión Digital de Servicios Integrados Terrestres (ISDB-T), también conocida como ARIB STD-B31. En junio de 2005, el Comité del Área de Tecnología de la Información (CATI) del Ministerio de Ciencia, Tecnología e Innovación de Brasil - MCTI aprobó la incorporación del Programa CI-Brasil, en el Programa Nacional de Microelectrónica (PNM). Los principales objetivos de la CI-Brasil son la formación de diseñadores de CIs, apoyar la creación de empresas de semiconductores enfocadas en proyectos de circuitos integrados dentro de Brasil, y la atracción de empresas de semiconductores interesadas en el diseño y desarrollo de circuitos integrados. El trabajo presentado en esta tesis se originó en el impulso único creado por la combinación del nacimiento de la televisión digital en Brasil y la creación del Programa de CI-Brasil por el gobierno brasileño. Sin esta combinación no hubiera sido posible realizar este tipo de proyectos en Brasil. Estos proyectos han sido un trayecto largo y costoso, aunque meritorio desde el punto de vista científico y tecnológico, hacia un Circuito Integrado brasileño de punta y de baja complejidad para DTV, con buenas perspectivas de economía de escala debido al hecho que al inicio de este proyecto, el estándar ISDB-T no fue adoptado por varios países como DVB-T. Durante el desarrollo del receptor ISDB-T propuesto en esta tesis, se observó que debido a las dimensiones continentales de Brasil, la DTTB no sería suficiente para cubrir todo el país con la señal de televisión digital abierta, especialmente para el caso de localizaciones remotas, apartadas de las regiones de alta densidad urbana. En ese momento, el Instituto de Investigación Eldorado e Idea! Sistemas Electrónicos, previeron que en un futuro cercano habría un sistema de distribución abierto para DTV de alta definición por satélite en Brasil. Con base en eso, el Instituto de Investigación Eldorado decidió que sería necesario crear un nuevo ASIC para la recepción de radiodifusión por satélite, basada el estándar DVB-S2. En esta tesis se analiza en detalle la Arquitectura y algoritmos propuestos para la implementación de un receptor ISDB-T de baja complejidad y frecuencia intermedia (IF) en un Circuito Integrado de Aplicación Específica (ASIC) CMOS. La arquitectura aquí propuesta se basa fuertemente en el algoritmo Computadora Digital para Rotación de Coordenadas (CORDIC), el cual es un algoritmo simple, eficiente y adecuado para implementaciones VLSI. El receptor hace frente a las deficiencias inherentes a las transmisiones por canales inalámbricos y los cristales del receptor. La tesis también analiza la metodología adoptada y presenta los resultados de la implementación. Por otro lado, la tesis también presenta la arquitectura y los algoritmos para un receptor DVB-S2 dirigido a la implementación en ASIC. Sin embargo, a diferencia del receptor ISDB-T, se introducen sólo los resultados preliminares de implementación en ASIC. Esto se hizo principalmente con el fin de tener una estimación temprana del área del die para demostrar que el proyecto en ASIC es económicamente viable, así como para verificar posibles errores en etapa temprana. Como en el caso de receptor ISDB-T, este receptor se basa fuertemente en el algoritmo CORDIC y fue un prototipado en FPGA. La metodología utilizada para el segundo receptor se deriva de la utilizada para el re[CA] La primera generació de Televisió Digital Terrestre (TDT) ha estat en servici durant més d'una dècada. En 2013, diversos països ja van completar la transició de la radiodifusió de televisió analògica a la digital, i la majoria van ser a Europa. A Amèrica del Sud, després de diversos estudis i assajos, Brasil va adoptar l'estàndard japonés amb algunes innovacions. Japó i Brasil van començar els servicis de Radiodifusió de Televisió Terrestre Digital (DTTB) al desembre de 2003 i al desembre de 2007, respectivament, utilitzant la Radiodifusió Digital amb Servicis Integrats de (ISDB-T), coneguda com a ARIB STD-B31. Al juny de 2005, el Comité de l'Àrea de Tecnologia de la Informació (CATI) del Ministeri de Ciència i Tecnologia i Innovació del Brasil (MCTI) va aprovar la incorporació del programa CI Brasil al Programa Nacional de Microelectrònica (PNM). Els principals objectius de CI Brasil són la qualificació formal dels dissenyadors de circuits integrats, el suport a la creació d'empreses de semiconductors centrades en projectes de circuits integrats dins del Brasil i l'atracció d'empreses de semiconductors centrades en el disseny i desenvolupament de circuits integrats. El treball presentat en esta tesi es va originar en l'impuls únic creat per la combinació del naixement de la televisió digital al Brasil i la creació del programa Brasil CI pel govern brasiler. Sense esta combinació no hauria estat possible realitzar este tipus de projectes a Brasil. Estos projectes han suposat un viatge llarg i costós, tot i que digne científicament i tecnològica, cap a un circuit integrat punter de baixa complexitat per a la TDT brasilera, amb bones perspectives d'economia d'escala perquè a l'inici d'este projecte l'estàndard ISDB-T no va ser adoptat per diversos països, com el DVB-T. Durant el desenvolupament del receptor de ISDB-T proposat en esta tesi, va resultar que, a causa de les dimensions continentals de Brasil, la DTTB no seria suficient per cobrir tot el país amb el senyal de TDT oberta, especialment pel que fa a les localitzacions remotes allunyades de les regions d'alta densitat urbana.. En este moment, l'Institut de Recerca Eldorado i Idea! Sistemes Electrònics van preveure que, en un futur pròxim, no hi hauria a Brasil un sistema de distribució oberta de TDT d'alta definició a través de satèl¿lit. D'acord amb això, l'Institut de Recerca Eldorado va decidir que seria necessari crear un nou ASIC per a la recepció de radiodifusió per satèl¿lit. basat en l'estàndard DVB-S2. En esta tesi s'analitza en detall l'arquitectura i els algorismes proposats per l'execució d'un receptor ISDB-T de Freqüència Intermèdia (FI) de baixa complexitat sobre CMOS de Circuit Integrat d'Aplicacions Específiques (ASIC). L'arquitectura ací proposada es basa molt en l'algorisme de l'Ordinador Digital de Rotació de Coordenades (CORDIC), que és un algorisme simple i eficient adequat per implementacions VLSI. El receptor fa front a les deficiències inherents a la transmissió de canals sense fil i els cristalls del receptor. Esta tesi també analitza la metodologia adoptada i presenta els resultats de l'execució. Es presenta el rendiment del receptor i es compara amb els obtinguts per mitjà de simulacions. D'altra banda, esta tesi també presenta l'arquitectura i els algorismes d'un receptor de DVB-S2 de cara a la seua implementació en ASIC. No obstant això, a diferència del receptor ISDB-T, només s'introdueixen resultats preliminars d'implementació en ASIC. Això es va fer principalment amb la finalitat de tenir una estimació primerenca de la zona de dau per demostrar que el projecte en ASIC és econòmicament viable, així com per verificar possibles errors en l'etapa primerenca. Com en el cas del receptor ISDB-T, este receptor es basa molt en l'algorisme CORDIC i va ser un prototip de FPGA. La metodologia utilitzada per al segon receptor es deriva de la utilitzada per al receptor IRodrigues De Lima, E. (2016). Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/61967TESI

Rapid Prototyping for Evaluating Vehicular Communications

[Abstract] This Thesis details the different elements of a rapid prototyping system able to implement and evaluate vehicular communications fast, according to the continuously evolving requirements of the industry. The system is basically composed of a testbed and a channel emulator, which allow evaluating communication transceivers in realistic vehicular scenarios. Two different testbeds are introduced: a generic 2x2 system and a vehicular platform. The former is used to compare and study space-time block coding (STBC) transmissions at 2.4 GHz over different indoor channels. The latter makes use of software transceivers whose performance is evaluated when they work under artificial high-speed Rayleigh-fading scenarios. To show the capabilities of both platforms, three software transceivers have been developed following the specifications for the physical layers of the standards IEEE 802.11p, IEEE 802.11a and IEEE 802.16e (Mobile WiMAX). The present work details the different elements that make up each transceiver and indicates how to connect them to the rest of the system to perform evaluation measurements. Finally, single-antenna and multi-antenna performances are measured thanks to the design and implementation of three FPGA-based channel emulators that are able to recreate up to seven different vehicular scenarios that include urban canyons, suburban areas and highways[Resumo] A presente Tese detalla os elementos necesarios para constituir un sistema basado en prototipado rápido capaz de levar a cabo e avaliar comunicacións vehiculares. O hardware do sistema está composto básicamente por unha plataforma de probas (testbed) e un emulador de canal, os cales permiten avaliar o rendemento de transceptores inartiamicos recreando diferentes escenarios vehiculares. Inicialmente, este traballo céntrase na descripción do hardware do sistema, detallando a construcción e proba dunha plataforma multi-antena e un testebed vehicular. Estos sistemas permitiron, respectivamente, estudar o comportamento de códigos STBC (space-time block codes) en interiores e medir o rendemento de tranceptores software ao traballar a distintas velocidades vehiculares en canais con desvaecemento Rayleigh. Tres transceptores software foron creados seguindo as especificacións das capas físicas dos estándares IEEE 802.11p, IEEE 802.11a e IEEE 802.16e (Mobile WiMAX). Este traballo detalla os diferentes componentes de cada transceptor, indicando cómo conectalos ao resto do sistema para realizar a avaliacition do seu rendemento. Dita avaliación realizouse coa axuda de tres emuladores de canal basados en tecnoloxía FPGA (Field Programmable Gate Array), os cales son capaces de recrear ata sete escenarios vehiculares distintos, incluindo cañóns urbanos, zonas suburbanas e autopistas.[Resumen] La presente Tesis detalla los elementos necesarios para constituir un sistema basado en prototipado rtiapido capaz de llevar a cabo y evaluar comunicaciones vehiculares. El hardware del sistema está compuesto por una plataforma de pruebas (testbed) y un emulador de canal, los cuales permiten evaluar el rendimiento de transceptores inaltiambricos recreando diferentes escenarios vehiculares. Inicialmente, este trabajo se centra en la descripcition del hardware del sistema, detallando la construccition y prueba de una plataforma multi-antena y un testebed vehicular. Estos sistemas han permitido, respectivamente, estudiar el comportamiento de ctiodigos STBC (space-time block codes) en interiores y medir el rendimiento en canal con desvanecimiento Rayleigh de tranceptores software a distintas velocidades vehiculares. Tres transceptores software han sido creados siguiendo las especificaciones de las capas físicas de los estandares IEEE 802.11p, IEEE 802.11a e IEEE 802.16e (Mobile WiMAX). Este trabajo detalla los diferentes componentes de cada transceptor, indicando ctiomo conectarlos al resto del sistema para realizar la evaluacition de su rendimiento. Dicha evaluacition se realiztio con la ayuda de tres emuladores de canal basados en FPGAs (Field Programmable Gate Array), los cuales son capaces de recrear comunicaciones multi-antena en hasta siete escenarios vehiculares distintos, incluyendo cañones urbanos, zonas suburbanas y autopistas

Channel Fading in Mobile Broadband Systems: Challenges and Opportunities

High-speed data signals transmitted over mobile broadband channels are seriously distorted by both time-varying effect and frequency-selective fading (FSF). These distortions introduce challenges since channel variances in both time-domain and frequency-domain form a two-dimensional channel matrix which is hard to estimate, but meanwhile provide opportunities for information security since all signals are directly encrypted by the channels which are adequately random over time, frequency and space. These challenges and opportunities are studied in this thesis as two parts. In the first part, we propose a novel time-varying channel estimation (TVCE) algorithm named piece-wise time-invariant approximation (PITIA) to estimate a typical type of mobile broadband channels - the high-speed train (HST) channels. PITIA customizes general time-varying channel models according to HST channels' specific features, and outperforms conventional TVCE algorithms by about 3-dB in terms of estimation error. In the second part, we propose the first physical-layer challenge-response authentication mechanism (PHY-CRAM) which uses the mobile broadband channels to prevent eavesdropping during authentication. Since pilots and reference signals are eliminated, eavesdroppers cannot demodulate credential information, while legitimate receivers use the channels' reciprocal property to cancel FSF. PITIA is evaluated by computer based simulations, and the effectiveness of PHY-CRAM is validated by prototyping and real-world experiments. Both pieces of works are built upon a unified system model and orthogonal frequency-division multiplexing (OFDM) modulation.Ph.D.College of Engineering and Computer ScienceUniversity of Michigan-Dearbornhttp://deepblue.lib.umich.edu/bitstream/2027.42/106584/1/Dissertation_Dan_Shan.pd

Signal Processing for Compressed Sensing Multiuser Detection

The era of human based communication was longly believed to be the main driver for the development of communication systems. Already nowadays we observe that other types of communication impact the discussions of how future communication system will look like. One emerging technology in this direction is machine to machine (M2M) communication. M2M addresses the communication between autonomous entities without human interaction in mind. A very challenging aspect is the fact that M2M strongly differ from what communication system were designed for. Compared to human based communication, M2M is often characterized by small and sporadic uplink transmissions with limited data-rate constraints. While current communication systems can cope with several 100 transmissions, M2M envisions a massive number of devices that simultaneously communicate to a central base-station. Therefore, future communication systems need to be equipped with novel technologies facilitating the aggregation of massive M2M. The key design challenge lies in the efficient design of medium access technologies that allows for efficient communication with small data packets. Further, novel physical layer aspects have to be considered in order to reliable detect the massive uplink communication. Within this thesis physical layer concepts are introduced for a novel medium access technology tailored to the demands of sporadic M2M. This concept combines advances from the field of sporadic signal processing and communications. The main idea is to exploit the sporadic structure of the M2M traffic to design physical layer algorithms utilizing this side information. This concept considers that the base-station has to jointly detect the activity and the data of the M2M nodes. The whole framework of joint activity and data detection in sporadic M2M is known as Compressed Sensing Multiuser Detection (CS-MUD). This thesis introduces new physical layer concepts for CS-MUD. One important aspect is the question of how the activity detection impacts the data detection. It is shown that activity errors have a fundamentally different impact on the underlying communication system than data errors have. To address this impact, this thesis introduces new algorithms that aim at controlling or even avoiding the activity errors in a system. It is shown that a separate activity and data detection is a possible approach to control activity errors in M2M. This becomes possible by considering the activity detection task in a Bayesian framework based on soft activity information. This concept allows maintaining a constant and predictable activity error rate in a system. Beyond separate activity and data detection, the joint activity and data detection problem is addressed. Here a novel detector based on message passing is introduced. The main driver for this concept is the extrinsic information exchange between different entities being part of a graphical representation of the whole estimation problem. It can be shown that this detector is superior to state-of-the-art concepts for CS-MUD. Besides analyzing the concepts introduced simulatively, this thesis also shows an implementation of CS-MUD on a hardware demonstrator platform using the algorithms developed within this thesis. This implementation validates that the advantages of CS-MUD via over-the-air transmissions and measurements under practical constraints