Viking '75 spacecraft design and test summary. Volume 2: Orbiter design

The design of the Viking orbiter spacecraft is described. System configuration, telecommunications, and guidance and control requirements are presented

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

A time-based approach for multi-GHz embedded mixed-signal characterization and measurement /

The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions.Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed

2020 NASA Technology Taxonomy

This document is an update (new photos used) of the PDF version of the 2020 NASA Technology Taxonomy that will be available to download on the OCT Public Website. The updated 2020 NASA Technology Taxonomy, or "technology dictionary", uses a technology discipline based approach that realigns like-technologies independent of their application within the NASA mission portfolio. This tool is meant to serve as a common technology discipline-based communication tool across the agency and with its partners in other government agencies, academia, industry, and across the world

Strategies towards high performance (high-resolution/linearity) time-to-digital converters on field-programmable gate arrays

Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required.Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested

Advanced Manned Launch System (AMLS) study

To assure national leadership in space operations and exploration in the future, NASA must be able to provide cost effective and operationally efficient space transportation. Several NASA studies and the joint NASA/DoD Space Transportation Architecture Studies (STAS) have shown the need for a multi-vehicle space transportation system with designs driven by enhanced operations and low costs. NASA is currently studying an advanced manned launch system (AMLS) approach to transport crew and cargo to the Space Station Freedom. Several single and multiple stage systems from air-breathing to all-rocket concepts are being examined in a series of studies potential replacements for the Space Shuttle launch system in the 2000-2010 time frame. Rockwell International Corporation, under contract to the NASA Langley Research Center, has analyzed a two-stage all-rocket concept to determine whether this class of vehicles is appropriate for the AMLS function. The results of the pre-phase A study are discussed