On Timing Model Extraction and Hierarchical Statistical Timing Analysis

In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and verification. For the three basic circuit types, combinational, flip-flop-based and latch-controlled, we propose methods to extract timing models which contain interfacing as well as compressed internal constraints. Using these compact timing models the runtime of full-chip timing analysis can be reduced, while circuit details from IP vendors are not exposed. We also propose a method to reconstruct the correlation between modules during full-chip timing analysis. This correlation can not be incorporated into timing models because it depends on the layout of the corresponding modules in the chip. In addition, we investigate how to apply the extracted timing models with the reconstructed correlation to evaluate the performance of the complete design. Experiments demonstrate that using the extracted timing models and reconstructed correlation full-chip timing analysis can be several times faster than applying the flattened circuit directly, while the accuracy of statistical timing analysis is still well maintained

Cell Library Creation using ALF

The design of Integrated Circuit (ASICs and SoCs) typically relies on the availability of a library consisting of predefined components called technology cells. Silicon vendors use proprietary formats to describe technology cells and macro modules in conjunction with numerous translators to feed technology library data to Electronic Design Automation (EDA) tools. Multiple grammar formats are used to represent various aspects of the cells in the same technology library, such as behavior for simulation, timing parameters for synthesis, physical data for layout, noise parameters for signal integrity checks, etc. In addition, most of these formats are highly tool-oriented and are not grammatically consistent. In this paper we will discuss the newly adopted IEEE 1603-2003 Advanced Library Format (ALF) standard which eliminates such drawbacks. This standard defines a grammar for accurate and comprehensive modeling of technology libraries and macro modules in order to bridge the growing gap between new design rules and the analysis required for complex high-end IC implementations

A CAD-oriented modeling approach of frequency-dependent behavior of substrate noise coupling for mixed-signal IC design

A simple, efficient CAD-oriented equivalent circuit modeling approach of frequency-dependent behavior of substrate noise coupling is presented. It is shown that the substrate exhibits significant frequency-dependent characteristics for high frequency applications using epitaxial layers on a highly doped substrate. Using the proposed modeling approach, circuit topographies consisting of only ideal lumped circuit elements can be synthesized to accurately represent the frequency response using y-parameters. The proposed model is well-suited for use in standard circuit simulators. The extracted model is shown to be in good agreement with rigorous 3D device simulation results. 1