79,626 research outputs found

    A Technology Aware Magnetic QCA NCL-HDL Architecture

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    Magnetic Quantum Dot Cellular Automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose a practicable clock structure for MQCA baptised "snake-clock", we stick to this while developing a system level Hardware Description Language (HDL) based description of an architectural block, and we suggest a delay insensitive Null Convention Logic (NCL) implementation for the magnetic case so that the "layout=timing" problem can be solved. Furthermore we include in our model aspects critically related to technology and real production, that is timing, power and layout, and we present the preliminary steps of our experiments, the results of which will be included in the architecture descriptio

    Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders

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    The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree dc up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magneti

    Identification of radiation induced dark current sources in pinned photodiode CMOS image sensors

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    This paper presents an investigation of Total Ionizing Dose induced dark current sources in Pinned PhotoDiodes (PPD) CMOS Image Sensors based on pixel design variations. The influence of several layout parameters is studied. Only one parameter is changed at a time enabling the direct evaluation of its contribution to the observed device degradation. By this approach, the origin of radiation induced dark current in PPD is localized on the pixel layout. The PPD peripheral STI does not seem to play a role in the degradation. The PPD area and an additional contribution independent on the pixel dimensions appear to be the main sources of the TID induced dark current increase

    Integrated and adaptive traffic signal control for diamond interchange : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Mechatronics Engineering at Massey University, Albany, New Zealand

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    New dynamic signal control methods such as fuzzy logic and artificial intelligence developed recently mainly focused on isolated intersection. Adaptive signal control based on fuzzy logic control (FLC) determines the duration and sequence that traffic signal should stay in a certain state, before switching to the next state (Trabia et al. 1999, Pham 2013). The amount of arriving and waiting vehicles are quantized into fuzzy variables and fuzzy rules are used to determine if the duration of the current state should be extended. The fuzzy logic controller showed to be more flexible than fixed controllers and vehicle actuated controllers, allowing traffic to flow more smoothly. The FLC does not possess the ability to handle various uncertainties especially in real world traffic control. Therefore it is not best suited for stochastic nature problems such as traffic signal timing optimization. However, probabilistic logic is the best choice to handle the uncertainties containing both stochastic and fuzzy features (Pappis and Mamdani 1977) Probabilistic fuzzy logic control is developed for the signalised control of a diamond interchange, where the signal phasing, green time extension and ramp metering are decided in response to real time traffic conditions, which aim at improving traffic flows on surface streets and highways. The probabilistic fuzzy logic for diamond interchange (PFLDI) comprises three modules: probabilistic fuzzy phase timing (PFPT) that controls the green time extension process of the current running phase, phase selection (PSL) which decides the next phase based on the pre-setup phase logic by the local transport authority and, probabilistic fuzzy ramp-metering (PFRM) that determines on-ramp metering rate based on traffic conditions of the arterial streets and highways. We used Advanced Interactive Microscopic Simulator for Urban and Non-Urban Network (AIMSUN) software for diamond interchange modeling and performance measure of effectiveness for the PFLDI algorithm. PFLDI was compared with actuated diamond interchange (ADI) control based on ALINEA algorithm and conventional fuzzy logic diamond interchange algorithm (FLDI). Simulation results show that the PFLDI surpasses the traffic actuated and conventional fuzzy models with lower System Total Travel Time, Average Delay and improvements in Downstream Average Speed and Downstream Average Delay. On the other hand, little attention has been given in recent years to the delays experienced by cyclists in urban transport networks. When planning changes to traffic signals or making other network changes, the value of time for cycling trips is rarely considered. The traditional approach to road management has been to only focus on improving the carrying capacity relating to vehicles, with an emphasis on maximising the speed and volume of motorised traffic moving around the network. The problem of cyclist delay has been compounded by the fact that the travel time for cyclists have been lower than those for vehicles, which affects benefit–cost ratios and effectively provides a disincentive to invest in cycling issues compared with other modes. The issue has also been influenced by the way in which traffic signals have been set up and operated. Because the primary stresses on an intersection tend to occur during vehicle (commuter) peaks in the morning and afternoon, intersections tend to be set up and coordinated to allow maximum flow during these peaks. The result is that during off-peak periods there is often spare capacity that is underutilised. Phasing and timings set up for peaks may not provide the optimum benefits during off-peak times. This is particularly important to cyclists during lunch-time peaks, when vehicle volumes are low and cyclist volumes are high. Cyclists can end up waiting long periods of time as a result of poor signal phasing, rather than due to the demands of other road users being placed on the network. The outcome of this study will not only reduce the traffic congestion during peak hours but also improve the cyclists’ safety at a typical diamond interchange

    Synchronization of multihop wireless sensor networks at the application layer

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    Time synchronization is a key issue in wireless sensor networks; timestamping collected data, tasks scheduling, and efficient communications are just some applications. From all the existing techniques to achieve synchronization, those based on precisely time-stamping sync messages are the most accurate. However, working with standard protocols such as Bluetooth or ZigBee usually prevents the user from accessing lower layers and consequently reduces accuracy. A receiver-to-receiver schema improves timestamping performance because it eliminates the largest non-deterministic error at the sender’s side: the medium access time. Nevertheless, utilization of existing methods in multihop networks is not feasible since the amount of extra traffic required is excessive. In this article, we present a method that allows accurate synchronization of large multihop networks, working at the application layer while keeping the message exchange to a minimum. Through an extensive experimental study, we evaluate the protocol’s performance and discuss the factors that influence synchronization accuracy the most.Ministerio de Ciencia y Tecnología TIN2006-15617-C0

    An aerogel Cherenkov detector for multi-GeV photon detection with low sensitivity to neutrons

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    We describe a novel photon detector which operates under an intense flux of neutrons. It is composed of lead-aerogel sandwich counter modules. Its salient features are high photon detection efficiency and blindness to neutrons. As a result of Monte Carlo (MC) simulations, the efficiency for photons with the energy larger than 1 GeV is expected to be higher than 99.5% and that for 2 GeV/cc neutrons less than 1%. The performance on the photon detection under such a large flux of neutrons was measured for a part of the detector. It was confirmed that the efficiency to photons with the energy >>1 GeV was consistent with the MC expectation within 8.2% uncertainty.Comment: 16 pages, 16 figures, submitted to Prog. Theor. Exp. Phy

    Integrated and Ecological Crop Protection (I/ECP)

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    Manual on integrated and ecological crop protectio

    Innovative teaching of IC design and manufacture using the Superchip platform

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    In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime
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