58 research outputs found

    Oversampling PCM techniques and optimum noise shapers for quantizing a class of nonbandlimited signals

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    We consider the efficient quantization of a class of nonbandlimited signals, namely, the class of discrete-time signals that can be recovered from their decimated version. The signals are modeled as the output of a single FIR interpolation filter (single band model) or, more generally, as the sum of the outputs of L FIR interpolation filters (multiband model). These nonbandlimited signals are oversampled, and it is therefore reasonable to expect that we can reap the same benefits of well-known efficient A/D techniques that apply only to bandlimited signals. We first show that we can obtain a great reduction in the quantization noise variance due to the oversampled nature of the signals. We can achieve a substantial decrease in bit rate by appropriately decimating the signals and then quantizing them. To further increase the effective quantizer resolution, noise shaping is introduced by optimizing prefilters and postfilters around the quantizer. We start with a scalar time-invariant quantizer and study two important cases of linear time invariant (LTI) filters, namely, the case where the postfilter is the inverse of the prefilter and the more general case where the postfilter is independent from the prefilter. Closed form expressions for the optimum filters and average minimum mean square error are derived in each case for both the single band and multiband models. The class of noise shaping filters and quantizers is then enlarged to include linear periodically time varying (LPTV)M filters and periodically time-varying quantizers of period M. We study two special cases in great detail

    Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers

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    Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile phone, enabling data to be sent over the distances needed to reach the receiver’s antenna. While linear operation is needed for transmitting WCDMA and OFDM signals, linear operation of a power amplifier is characterized by low power efficiency, and contributes to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier operation was considered for reducing power losses in a RF transmitter. A linear and efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu- lated, and subsequently amplified by a nonlinear device. Although in theory this approach offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting wideband signals causes problems in practical implementation: it requires high sampling rate by the digital hardware, which is needed for shaping large contents of a quantization noise induced by the modulator but also, the binary output from the modulator needs an RF power amplifier operating over very wide frequency band. This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved by optimizing structure of the modulator, and subsequent processing of an input signal’s samples in parallel. Independent from the above, a novel technique for reducing quan- tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The technique combines error pulse shaping and 3-level quantization for improving signal to noise ratio in a 2-level output. The improvement is achieved without the increase of a digital hardware’s sampling rate, which is advantageous also from the perspective of power consumption. The new method is explored in the course of analysis, and verified by simulated and experimental results. The process of RF signal conversion from the Cartesian to polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized envelope signal is designed and implemented. The new modulator takes an advantage of bandpass digital to analog conversion for simplifying the analog part of the modulator. A deformation of the pulsed RF signal in the experimental modulator is demonstrated to have an effect primarily on amplitude of the RF signal, which is correctable with simple predistortion

    Multiband Analog-to-Digital Conversion

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    The current trend in the world of digital communications is the design of versatile devices that may operate using several different communication standards in order to increase the number of locations for which a particular device may be used. The signal is quantized early on in the reciever path by Analog-to-Digital Converters (ADCs), which allows the rest of the signal processing to be done by low complexity, low power digital circuits. For this reason, it is advantageous to create an architecture that can quantize different bandwidths at different frequencies to suit several different communication protocols. This thesis outlines the design of an architecture that uses multiple ADCs in parallel to quantize several different bandwidths of a wideband signal. A multirate filter bank is then applied to approximate perfect reconstruction of the wideband signal from its subband parts. This highly flexible architecture is able to quantize signals of varying bandwidths at a wide range of frequencies by using identical hardware in every channel, which also makes for a simple design. A prototype for the quantizer used in each channel, a frequency-selective fourth-order sigma-delta (CA ) ADC, was designed and fabricated in a 0.5 pm CMOS process. This device uses a switched-capacitor technique to implement the frequency selection in the front-end of the CA ADC in each channel. Running at a 5MHz sample rate, the device can select any of the first sixteen 156.25kHz wide bands for conversion. Testing results for this fabricated part are also presented

    Multi-band Oversampled Noise Shaping Analog to Digital Conversion

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    Oversampled noise shaping analog to digital (A/D) converters, which are commonly known as delta-sigma (ΔΣ) converters, have the ability to convert relatively low bandwidth signals with very high resolution. Such converters achieve their high resolution by oversampling, as well as processing the signal and quantization noise with different transfer functions. The signal transfer function (STF) is typically a delay over the signal band while the noise transfer function (NTF) is designed to attenuate quantization noise in the signal band. A side effect of the NTF is an amplification of the noise outside the signal band. Thus, a digital filter subsequently attenuates the out-of-band quantization noise. The focus of this thesis is the investigation of ΔΣ architectures that increase the bandwidth where high resolution conversion can be achieved. It uses parallel architectures exploiting frequency or time slicing to meet this objective. Frequency slicing involves quantizing different portions of the signal frequency spectrum using several quantizers in parallel and then combining the results of the quantizers to form an overall result. Time slicing involves quantizing various groups of time domain signal samples with different quantizers in parallel and then combining the results of the quantizers to form an overall output. Several interesting observations can be made from this general perspective of frequency and time slicing. Although the representation of a signal are completely equivalent in time or frequency, the thesis shows that this is not the case for known frequency and time sliced A/D architectures. The performance of such systems under ideal conditions are compared for PCM as well as for ΔΣ A/D converters. A multi-band frequency sliced architecture for delta-sigma conversion is proposed and its performance is included in the above comparison. The architecture uses modulators which realize different NTFs for different portions of the signal band. Each band is converted in parallel. A bank of FIR filters attenuates the out of-band noise for each band and achieves perfect reconstruction of the signal component. A design procedure is provided for the design of the filter bank with reduced computational complexity. The use of complex NTFs in the multi-band ΔΣ architecture is also proposed. The peformance of real and complex NTFs is compared. Performance evaluations are made for ideal systems as well as systems suffering from circuit implementation imperfections such as finite opamp gain and mismatched capacitor ratios

    Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

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    The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

    Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

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    The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

    Extended frequency-band-decomposition sigma–delta A/D converter

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    Parallelism can be used to increase the bandwidths of ADC converters based on sigma–delta modulators. Each modulator converts a part of the input signal band and is followed by a digital filter. Unfortunately, solutions using bandpass sigma–delta modulators are very sensitive to the position of the modulators' central frequencies. This paper shows the feasibility of a frequency-band-decomposition (FBD) ADC using continuous time bandpass sigma–delta modulators, even in the case of large analog mismatches. The major benefit of such a solution, called extended-frequency-band-decomposition (EFBD) is its low sensitivity to analog parameters. For example, a relative error in the central frequencies of 4% can be accepted without significant degradation in the performance (other published FBD ADCs require a precision of the central frequencies better than 0.1%). This paper will focus on the performance which can be reached with this system, and the architecture of the digital part. The quantization of coefficients and operators will be addressed. It will be shown that a 14 bit resolution can be theoretically reached using 10 sixth-order bandpass modulators at a sampling frequency of 800 MHz which results in a bandwidth of 80 MHz centered around 200 MHz (the resolution depends on the effective quality factor of the filters of the analog modulators)

    A 8 mW 72 dB Sigma Delta-modulator ADC with 2.4 MHz BW in 130 nm CMOS

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    A double-sampling sigma delta-ADC with bilinear integrators and a 7-level quantizer is presented. It achieves third order noise shaping with a second order modulator through quantization noise-coupling. The modulator is integrated in a 130 nm CMOS technology. For a clock frequency of 48 MHz and an oversampling ratio of 20 (2.4 MHz signal bandwidth), it achieves 72 dB DR and 68 dB SNR. The prototype consumes 8 mW from a 1.2 V voltage supply

    Oversampling PCM techniques and optimum noise shapers for quantizing a class of nonbandlimited signals

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