Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

Low-power high-speed ADC design techniques in scaled CMOS process

The power consumption of a single-channel successive approximation register (SAR) analog-to-digital (ADC) tends to linearly increase with its sampling rate (f[subscript s]), when f[subscript s] is small. However, when f[subscript s] passes a certain point for a given technology node, the ADC power P increases at much higher rate and the normalized power efficiency (P/f[subscript s]) starts to degrade rapidly. To enhance the conversion speed of SAR ADC, while maintaining a good power efficiency, this thesis presents speed-enhancing techniques for SAR ADC in nano-scale CMOS technologies. First chapter presents a 2b/cycle hybrid SAR architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, 2b/cycle conversion technique can boost the f[subscript s] of the ADC without any additional DAC arrays. High-speed ADCs can boost the conversion speed not only by increasing the f[subscript s] of a single-channel ADC, but also by time-interleaving multiple ADC sub-channels running at a lower rate. For an N-channel time-interleaved (TI) SAR ADC operating at f[subscript s], each sub-SAR channel only needs to operate at f[subscript s]=N. Therefore, each sub-SAR can operate in the linear power versus speed region, leading to a significant power saving compared to a single-channel ADC running at the same sampling rate. Despite of its power efficiency, TI-ADC suffers from mismatches among sub-ADC channels, including gain, offset, and timing mismatches. Among them, timing skew is one of the most difficult errors to calibrate as it is nontrivial to extract and its induced error depends on both the frequency and the amplitude of the input signal. Second chapter of this thesis presents a TI-SAR with a fast variance-based timing-skew calibration technique. It uses a single-comparator based window detector (WD) to calibrate the timing skew. The WD suppresses variance estimation errors and allow precise variance estimation from a significantly small number of samples. It has low-hardware cost and orders of magnitude faster convergence speed compared to prior variance-based timing-skew calibration technique. The last chapter presents another TI-SAR with mean absolute deviation (MAD) based timing-skew calibration technique. In addition to all the advantages presented with the fast variance-based timing-skew calibration technique, the proposed technique further reduces the digital computation power by 50% by eliminating the squaring operations, which are essential in variance-based calibration techniqueElectrical and Computer Engineerin

8-bit 1 Gs/s Adc Architecture And 4-bit Flash Adc For +10 Gs/s Time Interleaved Adc In 65nm Cmos Technology

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2015Thesis (M.Sc.) -- İstanbul Technical University, Instıtute of Science and Technology, 2015Haberleşme sistemlerinin veri aktarım sıklıkları ve bant genişlikleri sürekli olarak artmaktadır. Sayısal yarıiletken teknolojilerindeki gelişmeler, haberleşme sistemlerindeki işaret işleme kısımlarını sayısal domenine almıştır. Sayısal işaret işlemenin avantajları, ideal olmayan durumlara yüksek tolerans, gerçekleme kolaylığı, bir fonksiyonu gerçeklemek için gereken alanın dolayısıyla maliyetin düşük olması ve yeni teknolojilere taşınabilme olarak sayılabilir. Bu avantajlardan faydalanmak için analog işaretleri sayısal domene almada köprü görevi görecek yüksek hızlı analog-sayısal dönüştürücülere(ADC) ihtiyaç vardır. Kablolu ve kablosuz haberleşme teknolojilerinde 10 GHz'yi de aşan bant genişlikleri tek kanallı ADCleri bu iş için elverişsiz kılmaktadır. Zaman aralıklı ADCler gerek ulaşabilecekleri dönüştürme hızı gerek güç verimliliği açısından iyi bir aday olarak karşımıza çıkar. Zaman aralıklama, tek kanallı eş ADClerin sıra ile kullanılması esasına dayanmaktadır. Sıradaki örneği alan ADC, sıra tekrar kendisine gelene kadar bu örneği dönüştürür. Dolayısıyla toplam dönüştürme hızı, tek bir dönüştürücünün hızı ile kanal sayısının çarpımı kadar olmaktadır. Bu şekilde yüksek dönüştürme hızları elde edilebilir. Ayrıca bu şekilde tek kanal ADCler daha fazla hız elde etmek için güç bakımından verimsiz oldukları noktalara itilmez ve daha verimli yapılar ortaya çıkar. Zaman aralıklı ADClerdeki kanal uyumsuzlukları performansı düşürmektedir. Bu hatalar temel olarak dengesizlik, kazanç ve zamanlama uyumsuzluklarından ileri gelmektedir. Zamanlama hataları kestirilmeleri ve düzeltilmeleri noktasında diğerlerinden daha zorludur ve bu durum yüksek frekanslarda daha da zorlaşmaktadır. Zaman aralıklı ADClerdeki zamanlama hatalarının kestirilmeleri ve düzeltilmeleri güncel bir araştırma konusu teşkil etmektedir. Hataların kalibrasyonu ön planda veya arka planda yapılabilir. Arka planda yapılan kalibrasyon sistemin işlerliği ile ilgili herhangi bir sıkıntı yaratmaması ve değişen çevre şartlarına uyum sağlayabilme esnekliği açısından daha avantajlıdır. Zaman aralıklama hataları frekans spektrumunda çıkıntılar(spur) oluşturmaktadır. Bu çıkıntılar, güçlü olmaları durumunda alıcı kısmındaki devreleri sıkıştırma noktasına iterek modülasyonlu işaretlerin sezilmesini zorlaştırabilir veya giriş işaretini tamamen engelleyebilirler. Dolayısıyla kanal uyumsuzluk hataları özellikle kablosuz haberleşme sistemleri için sorun teşkil etmektedir. Bu sorunlardan kurtulmak için kanalları rastgele kullanmaya dayanan bir teknik önerilmiştir. Bu teknik ile kanallardan kaynaklanan hatalar çıkışa rastgele bir sırayla etki yaptıklarından gürültü gibi bir karaktere geçerler. Dolayısıyla frekans spektrumundaki çıkıntılar söndürülmüş olur. Tekniğin bir diğer avantajı arka planda çalışmasıdır. Ancak dikkat edilmelidir ki bu teknik bir hata düzeltme tekniği değildir, dolayısıyla sistemin işaretgürültü oranını iyileştirmemektedir. Kanal uyumsuzluk hatalarının kestirilmesi gibi, saat işaretlerinin dağıtılması da artan kanal sayısı ile zorlaşmaktadır. Ayrıca yüksek kanal sayısına sahip olan zaman aralıklı ADClerde saat işareti dağıtımının tükettiği güç yüksek seviyelere ulaşabilir. Belli bir dönüştürme hızı için kanal sayısını düşük tutmak ise kanal ADClerinin dönüştürme hızlarını arttırmak ile mümkündür. ADClerin hızları yüksek tutulurken aynı zamanda güç verimliliği de yüksek tutulmalıdır. Bu hedefler doğrultusunda 8-bit 1 GS/s bir çevrimde birden fazla bit dönüştüren bir SAR ADC yapısı önerilmiştir. Bir çevrimde birden fazla bit dönüştüren SAR ADCler, tek kanalda yüksek hızlara çıkmak konusunda sıkça kullanılan bir yöntem olarak karşımıza çıkmaktadır. Bunun yanında ilk üç en anlamlı bit bir flash ADC ile dönüştürüldüğünden önemli hız kazanımları elde edilir. Flash ADC çıkışında bir kod çözücü yapısı kullanılmaması da zaman kazanımında etkilidir. Önerilen ADC yapısında özgün bir dönüştürme algoritması kullanılmaktadır. Algoritma temel olarak, dönüştürme fazlarına fazladan seviyeler eklemek ve fazların aralıklarını kesiştirmek sureti ile devre bloklarının hata toleranslarını arttırmasına dayanmaktadır. Bu nedenle herhangi bir kalibrasyon sistemine ihtiyaç duyulmaz dolayısıyla güç tüketimi azaltılabilir. Bu yapının gerçeklenebilmesi için çoklu seviye üreten bir ön kuvvetlendirici önerilmiştir. Önerilen ön kuvvetlendirici yapısı nedeniyle, algoritmadaki farklı fazlar için tek bir ön kuvvetlendirici kullanılabilmektedir. Bu sayede farklı ön kuvvetlendiricilerden kaynaklanacak dengesizlik uyumsuzluklarının da önüne geçilmiş olur. Yüksek hızlı veri dönüştürücülerin gerçeklenmesindeki en etkili devre bloğu, kendisi de 1 bitlik bir ADC olarak sayılabilecek karşılaştırıcı devreleridir. Karşılaştırıcı devresinin hızı, doğruluğu ve güç tüketimi bir ADCnin ilgili performans parametrelerini doğrudan etkilemektedir. Yüksek karşılaştırma hızlı özgün bir gömülü ön kuvvetlendiricili karşılaştırıcı devre önerilmiştir. Yapı geleneksel dinamik sezme kuvvetlendiricisi devresi temel alınarak tasarlanmıştır. Ek olarak giriş farksal kuvvetlendirici bölümüne bir statik akım kaynağı bağlanmıştır. Bu şekilde dinamik karşılaştırıcı yapısına ön kuvvetlendirici gömülmüş olur. Yapı geleneksel yapılara nazaran, hız, dengesizlik, güç tüketimi ve geri tepme gürültüsü açısından iyileştirmeler içermektedir. 8-bit 1 GS/s bir çevrimde birden fazla bit dönüştüren SAR ADC yapısı, ilk 3 biti olabildiğince hızlı dönüştürmek için bir flash ADC yapısı kullanmaktadır. Flash ADC yapılarının önemli hız avantajlarına rağmen, karşılaştırıcı devrelerin dengesizlik ve geri tepme gürültüsü performansı düşürmektedir. Önerilen gömülü ön kuvvetlendiricili karşılaştırıcı devresi dengesizlik performansını ve geri tepme gürültüsünü iyileştirmektedir. Ancak geri tepme gürültüsünden kaynaklanan hataları tam olarak çözmek adına, referans gerilimleri de giriş işaretleri gibi örneklenebilir. Bu teknik ile karşılaştırıcı geri tepme gürültüsünün giriş ve referans gerilimi üzerindeki etkisi eşitlenmekte ve geri tepme gürültüsünün etkisi bertaraf edilmektedir. ADC girişleri örneklenerek geldiğinden ve örnekleme devrelerindeki bir hata doğrudan ADCye iletileceğinden bu devrelerin performansı çok önemlidir. Çapraz bağlamalı anahtar tekniği kullanılarak anahtarların doğrusallığı iyileştirilmiştir. Aynı zamanda çapraz bağlama tekniği anahtar yük enjeksiyonu hatasını giriş işaretinden bağımsız hale getirmektedir. Bu durum, yukarıda bahsedilen referans örnekleme tekniği ile birleştirildiğinde flash ADC için önemli bir doğruluk iyileştirmesi sağlamaktadır. ADC blokları ST Microelectronics 65 nm CMOS teknolojisinde tasarlanmış ve serimleri yapılmıştır. Serim sonrası benzetim sonuçları tasarımların ve kullanılan tekniklerin doğruluğunu göstermektedir. Tasarlanan ADC Haziran 2015'de üretime yollanmıştır. Kasım 2015'de ölçümlere başlanması planlanmaktadır.Data rate of communication systems constantly increasing . Rapid scaling of digital semiconductor technologies has moved the signal processing of these systems to digital domain. Therefore high-speed ADCs are required to form the bridge to take the analog signals in digital domain. Data rates exceeding 10 Gbps makes the use of single channel ADCs unfeasible on this purpose. A power efficient solution is time-interleaving. Time-interleaving relaxes the speed requirements on single channel ADCs and lets designers to focus on power efficiency of the ADC. Channel mismatches in time-interleaved ADCs causes performance degradation. Errors arise mainly due to offset, gain and timing mismatch of channels. Among them, timing error is the most problematic since estimation of timing errors becomes more cumbersome in high-frequencies. Estimation and correction of timing errors in time-interleaved ADCs are hot topics of research. Calibration of errors can be on background or on foreground. Background calibration is more desirable since it allows system to adapt to changing conditions while not hindering the operation of the ADC. Time interleaving errors generate spurs on the spectrum. Spurs are problematic for the wireless communication systems, since they may block the input signal. In order to extinguish the spurs a channel randomization technique is proposed. Technique is based on randomly taking one of the ADC channels to make the errors of the channels noise-like term. It is advantageous since it works on background. Technique maintains a spur-free spectrum however does not improve the SNR of the system. Estimation of channel mismatch errors and clock distribution in a time-interleaved ADC becomes tedious as the number of channels increase. In order to keep the channel number low, channels should be fast while being power efficient. To satisfy this task, an 8-bit 1 GS/s multi-bit per cycle ADC is proposed. ADC employs a novel search algorithm based on redundancy. No calibration scheme required thanks to the algorithm therefore the power efficiency of the system can be increased. In order to realize the multi-bit per cycle structure, a multiple-threshold generation preamp is proposed. Comparators are the most important part of an ADC. Comparator specifications such as speed, accuracy and power consumption directly affect the relative specifications of the whole ADC. A novel latch with embedded preamp is proposed. Novel structure has latch regeneration time, offset, power consumption and kickback noise improvements over the conventional structures. 8-bit 1 GS/s multi-bit per cycle SAR ADC employs a flash ADC to perform the coarse conversion benefit from its speed. Although flash ADCs are fast, offset and kickback noise of comparators can penalize their accuracy. Proposed latch with embedded preamp improves the offset performance. To solve the kickback issue, reference voltages of the flash ADC are sampled. This technique is based on equalizing the kickback for both input and reference voltages therefore eliminating the effect. Sampling network of the ADC is critically important since any error made in the sampling phase directly passes to the ADC. Bootstrapped switches are used to improve the linearity of the switches. By using bootstrap switches, charge injection can be made signal independent. If it is combined with the reference sampling technique used in flash ADC, effects of charge injection can be diminished significantly. ADC blocks are designed and laid out in ST Microlectronics 65 nm process. Postlayout simulations have proven the efectiveness of the proposed techniques and blocks. Tape-out was done in July 2015. Measurements is expected to take place in November 2015.Yüksek LisansM.Sc

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

Design techniques for low-power SAR ADCs in nano-scale CMOS technologies

This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparator’s power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparator’s offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Electrical and Computer Engineerin

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH