Worst-Case Communication Time Analysis for On-Chip Networks with Finite Buffers

Network-on-Chip (NoC) is the ideal interconnection architecture for many-core systems due to its superior scalability and performance. An NoC must deliver critical messages from a realtime application within specific deadlines. A violation of this requirement may compromise the entire system operation. Therefore, a series of experiments considering worst-case scenarios must be conducted to verify if deadlines can be satisfied. However, simulation-based experiments are time-consuming, and one alternative is schedulability analysis. In this context, this work proposes a schedulability analysis to accelerate design space exploration in real-time applications on NoC-based systems. The proposed worstcase analysis estimates the maximum latency of traffic flows assuming direct and indirect blocking. Besides, we consider the size of buffers to reduce the analysis’ pessimism. We also present an extension of the analysis, including self-blocking. We conduct a series of experiments to evaluate the proposed analysis using a cycle-accurate simulator. The experimental results show that the proposed solution presents tighter results and runs four orders of magnitude faster than the simulation.N/

Results From the Long-Term Inmate Survey: Focus on Child Abuse Histories

This report of long-term inmates in Alaska correctional facilities attempts to describe the childhood experiences of a sample of long-term inmates, address the "cycle of abuse" issue; and present the correlates of abuse which may impact the pattern of offending or inmate functioning. Over 80 percent of long-term inmates report having been physically abused as children; over 65 percent report having suffered neglect.Alaska Department of CorrectionsResults from the Long Term Inmate Study: Focus on Child Abuse Histories / Incidence of Child Abuse and the Relationship to Criminality / Measuring Child Abuse and Neglect: A Review of Methods / Survey Methods and Administration / An Assessment of Survey Biases / Tables to Support Profile Analysis / Personal Interview Administration and Results / Correlates of Abus

Nitric oxide modulates expression of extracellular matrix genes linked to fibrosis in kidney mesangial cells

Mesangial cells are thought to be important mediators of glomerular inflammation and fibrosis. Studies have established a direct role for nitric oxide (NO) in the regulation of gene expression in mesangial cells. Representational difference analysis was used to investigate changes in gene expression elicited by the treatment of S-nitroso-L-glutathione in rat mesangial cells. Seven upregulated and 11 downregulated genes were identified. Four out of 11 downregulated genes (connective tissue growth factor, thrombospondin-1, collagen type I all and collagen type I alpha 2) are known to be linked to inflammation and fibrosis. Results were verified across species in mesangial cells treated with a series of NO donors using Northern blot analysis, quantitative real-time PCR and protein analysis methods. Induction of endogenous NO production by cytokine stimulation also triggered regulation of the genes. One example gene, connective tissue growth factor, was studied at the promoter level. Promoter-reporter gene studies in mesangial cells demonstrated that NO acts at the transcriptional level to suppress gene expression. Our results reveal a complex role of NO in regulating gene expression in mesangial cells and suggest an antifibrotic potential for NO

Fast, Accurate and Detailed NoC Simulations

Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy