AN EFFICIENT ERROR DETECTION AND CORRECTION METHOD FOR TIMING ERRORS

Timing errors are an important concern in nanometer CMOS technologies. A promising way to overcome the timing errors is the development of error detection and correction techniques. A local error detection and correction technique is done in this work. It is based on a new bit flipping flip flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip flop. No extra circuitry is inserted in the design. Timing errors are identified and corrected within a single cycle and hence design complexity is reduced which results in reduced power consumption and low silicon area when compared to the earlier designs

Sensitivity Evaluation Method for Aerospace Digital Systems with Collaborative Hardening

Complexity of current digital systems and circuits involves new challenges in the field of hardening and measuring circuits sensitivity under SEEs. In this work, a new solution for evaluating the SEU sensitivity of space systems based on using programmable logic devices is proposed. This solution is able to perform a deep analysis of fault effects in systems with hardware functionality distribution, taking into account the high complexity of the hardware nodes (complex programmable logic devices) and their collaborative hardening properties

Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths

It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. In this paper, we proposed an output remapping technique to reduce SER of critical paths. Experimental results show up to about 20X increase in Qcritical. So the SER is reduced significantly. This method does not introduce any delay penalty. The area/power overhead is limited as well. The output remapping method is based on our novel glitch width model. The analysis shows that output remapping technique works well along with technology scaling