2,680 research outputs found
Throughput of Streaming Applications Running on a Multiprocessor Architecture
We study the timing behaviour of streaming applications running on a multiprocessor architecture. Dependencies are derived between the application throughput and the timing characteristics of the processors and communication. Four different processor organizations that strongly influenced the results are considered and compared
Architecture Design Space Exploration for Streaming Applications Through Timing Analysis
In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application's throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations
Run-time Spatial Mapping of Streaming Applications to Heterogeneous Multi-Processor Systems
In this paper, we define the problem of spatial mapping. We present reasons why performing spatial mappings at run-time is both necessary and desirable. We propose what is—to our knowledge—the first attempt at a formal description of spatial mappings for the embedded real-time streaming application domain. Thereby, we introduce criteria for a qualitative comparison of these spatial mappings. As an illustration of how our formalization relates to practice, we relate our own spatial mapping algorithm to the formal model
A Simple Multiprocessor Management System for Event-Parallel Computing
Offline software using TCP/IP sockets to distribute particle physics events
to multiple UNIX/RISC workstations is described. A modular, building block
approach was taken, which allowed tailoring to solve specific tasks efficiently
and simply as they arose. The modest, initial cost was having to learn about
sockets for interprocess communication. This multiprocessor management software
has been used to control the reconstruction of eight billion raw data events
from Fermilab Experiment E791.Comment: 10 pages, 3 figures, compressed Postscript, LaTeX. Submitted to NI
Heterogeneous processor pipeline for a product cipher application
Processing data received as a stream is a task commonly performed by modern
embedded devices, in a wide range of applications such as multimedia
(encoding/decoding/ playing media), networking (switching and routing), digital
security, scientific data processing, etc. Such processing normally tends to be
calculation intensive and therefore requiring significant processing power.
Therefore, hardware acceleration methods to increase the performance of such
applications constitute an important area of study. In this paper, we present
an evaluation of one such method to process streaming data, namely
multi-processor pipeline architecture. The hardware is based on a
Multiple-Processor System on Chip (MPSoC), using a data encryption algorithm as
a case study. The algorithm is partitioned on a coarse grained level and mapped
on to an MPSoC with five processor cores in a pipeline, using specifically
configured Xtensa LX3 cores. The system is then selectively optimized by
strengthening and pruning the resources of each processor core. The optimized
system is evaluated and compared against an optimal single-processor System on
Chip (SoC) for the same application. The multiple-processor pipeline system for
data encryption algorithms used was observed to provide significant speed ups,
up to 4.45 times that of the single-processor system, which is close to the
ideal speed up from a five-stage pipeline
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