Versatile FPGA architecture for skein hashing algorithm

Digital communications and data storage are expanding at fast rates, increasing the need for advanced cryptographic standards to validate and provide privacy for that data. One of the basic components commonly used in information security systems is cryptographic hashing. Cryptographic hashing involves the compression of an arbitrary block of data into a fixed-size string of bits known as the hash value. These functions are designed such that it is computationally infeasible to determine a message that results in a given hash value. It should also be infeasible to find two messages with the same hash value and to change a message without its hash value being changed. Some of the most common uses of these algorithms are digital signatures, message authentication codes, file identification, and data integrity. Due to developments in attacks on the Secure Hash Standard (SHS), which includes SHA-1 and SHA-2 (SHA-224, SHA-256, SHA-384, SHA-512), the National Institute of Standards and Technology (NIST) will be selecting a new hashing algorithm to replace the current standards. In 2008, 64 algorithms were entered into the NIST competition and in December 2010, five finalists were chosen. The final candidates are BLAKE, Keccak, Gr{o}stl, JH, and Skein. In 2012, one of these algorithms will be selected for the Secure Hash Algorithm 3 (SHA-3). This thesis focuses on the development of a versatile hardware architecture for Skein that provides both sequential and tree hashing functions of Skein. The performance optimizations rely heavily on pipelined and unrolled architectures to allow for simultaneous hashing of multiple unique messages and reduced area tree hashing implementations. Additional result of this thesis is a comprehensive overview of the newly developed architectures and an analysis of their performance in comparison with other software and hardware implementations

Performance analysis of a scalable hardware FPGA Skein implementation

Hashing functions are a key cryptographic primitive used in many everyday applications, such as authentication, ensuring data integrity, as well as digital signatures. The current hashing standard is defined by the National Institute of Standards and Technology (NIST) as the Secure Hash Standard (SHS), and includes SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 . SHS\u27s level of security is waning as technology and analysis techniques continue to develop over time. As a result, after the 2005 Cryptographic Hash Workshop, NIST called for the creation of a new cryptographic hash algorithm to replace SHS. The new candidate algorithms were submitted on October 31st, 2008, and of them fourteen have advanced to round two of the competition. The competition is expected to produce a final replacement for the SHS standard by 2012. Multi-core processors, and parallel programming are the dominant force in computing, and some of the new hashing algorithms are attempting to take advantage of these resources by offering parallel tree-hashing variants to the algorithms. Tree-hashing allows multiple parts of the data on the same level of a tree to be operated on simultaneously, resulting in the potential to reduce the execution time complexity for hashing from O(n) to O(log n). Designs for tree-hashing require that the scalability and parallelism of the algorithms be researched on all platforms, including multi-core processors (CPUs), graphics processors (GPUs), as well as custom hardware (ASICs and FPGAs). Skein, the hashing function that this work has focused on, offers a tree-hashing mode with different options for the maximum tree height, and leaf node size, as well as the node fan-out. This research focuses on creating and analyzing the performance of scalable hardware designs for Skein\u27s tree hashing mode. Different ideas and approaches on how to modify sequential hashing cores, and create scalable control logic in order to provide for high-speed and low-area parallel hashing hardware are presented and analyzed. Equations were created to help understand the expected performance and potential bottlenecks of Skein in FPGAs. The equations are intended to assist the decision making process during the design phase, as well as potentially provide insight into design considerations for other tree hashing schemes in FPGAs. The results are also compared to current sequential designs of Skein, providing a complete analysis of the performance of Skein in an FPGA

Study of OpenCL processing models for FPGA device

In our study, we present the results of the implementation of SHA-512 algorithm in FPGA. The distinguished element of our work is that we conducted the work using OpenCL for FPGA which is a relatively new development method for reconfigurable logic. We examine the loop unrolling; as the OpenCL performance optimisation method, and compare the efficiency of the different kernel implementation types: NDRange, Single-Work Item, and SIMD kernels. In conclusions, we compare metrics of the created FPGA accelerator to the corresponding GPGPU solutions. Also, our paper is accompanied by the source code repository to allow the reader to follow and extend our survey

FPGA design and performance analysis of SHA-512, whirlpool and PHASH hashing functions

Hashing functions play a fundamental role in modern cryptography. Such functions process data of finite length and produce a small fixed size output referred to as a digest or hash. Typical applications of these functions include data integrity verification and message authentication schemes. With the ever increasing amounts of data that needs to be hashed, the throughput of hashing functions becomes an important factor. This work presents and compares high performance FPGA implementations of SHA- 512, Whirlpool and a recently proposed parallelizable hash function, PHASH. The novelty of PHASH is that it is able to process multiple data blocks at once, making it suitable for achieving ultra high-performance. It utilizes the W cipher, as described in Whirlpool, at its core. The SHA (SHA-0, SHA-1, SHA-2) family of functions is one of the first widely accepted standards for hashing. According to currently published literature, the fastest SHA-512 (a variant of SHA-2) implementation achieves a throughput of 1550 Mbps. A recently introduced hashing function, Whirlpool, provides comparable security to SHA- 512 and is able to achieve much better performance. According to currently published literature, the fastest Whirlpool implementation achieves a throughput of 4896 Mbps. The proposed PHASH hash function greatly outperforms both SHA-512 and Whirlpool. All implementations are targeted for the state-of-the-art Xilinx Virtex-5 LX330 FPGA. The SHA-512 implementation attains a throughput of 1828 Mbps, and Whirlpool attains 7687 Mbps. PHASH achieves a throughput over 15 Gbps using a singleWcipher instance. Using 8 W cipher instances a throughput over 100 Gbps is achieved and 16 instances provide a throughput over 182 Gbps

A Standalone FPGA-based Miner for Lyra2REv2 Cryptocurrencies

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2. Several properties of the aforementioned algorithm are exploited in order to optimize the design. In addition, an FPGA-based hardware implementation of a standalone miner for Lyra2REv2 on a Xilinx Multi-Processor System on Chip is presented. The proposed Lyra2REv2 miner is shown to be significantly more energy efficient than both a GPU and a commercially available FPGA-based miner. Finally, we also explain how the simplified Lyra2 and Lyra2REv2 architectures can be modified with minimal effort to also support the recent Lyra2REv3 chained hashing algorithm.Comment: 13 pages, accepted for publication in IEEE Trans. Circuits Syst. I. arXiv admin note: substantial text overlap with arXiv:1807.0576

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

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On the Exploitation of a High-throughput SHA-256 FPGA Design for HMAC

High-throughput and area-efficient designs of hash functions and corresponding mechanisms for Message Authentication Codes (MACs) are in high demand due to new security protocols that have arisen and call for security services in every transmitted data packet. For instance, IPv6 incorporates the IPSec protocol for secure data transmission. However, the IPSec's performance bottleneck is the HMAC mechanism which is responsible for authenticating the transmitted data. HMAC's performance bottleneck in its turn is the underlying hash function. In this article a high-throughput and small-size SHA-256 hash function FPGA design and the corresponding HMAC FPGA design is presented. Advanced optimization techniques have been deployed leading to a SHA-256 hashing core which performs more than 30% better, compared to the next better design. This improvement is achieved both in terms of throughput as well as in terms of throughput/area cost factor. It is the first reported SHA-256 hashing core that exceeds 11Gbps (after place and route in Xilinx Virtex 6 board)

High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs

Secure hash algorithms (SHAs) are important components of cryptographic applications. SHA performance on central processing units (CPUs) is slow, therefore, acceleration must be done using hardware such as Field Programmable Gate Arrays (FPGAs). Considerable work has been done in academia using FPGAs to accelerate SHAs. These designs were implemented using Hardware Description Language (HDL) based design methodologies, which are tedious and time consuming. High Level Synthesis (HLS) enables designers to synthesize optimized FPGA hardware from algorithm specifications in programming languages such as C/C++. This substantially reduces the design cost and time. In this thesis, the Altera SDK for OpenCL (AOCL) HLS tool was used to synthesize the SHAs on FPGAs and to explore the design space of the algorithms. The results were evaluated against the previous HDL based designs. Synthesized FPGA hardware performance was comparable to the HDL based designs despite the simpler and faster design process

A State-of-the-Art Survey for IoT Security and Energy Management based on Hashing Algorithms

The Internet of Things (IoT) has developed as a disruptive technology with wide-ranging applications across several sectors, enabling the connecting of devices and the acquisition of substantial volumes of data. Nevertheless, the rapid expansion of networked gadgets has generated substantial apprehensions pertaining to security and energy administration. This survey paper offers a detailed examination of the present state of research and advancements in the field of Internet of Things (IoT) security and energy management. The work places special emphasis on the use of hashing algorithms in this context. The security of the Internet of Things (IoT) is a crucial element in safeguarding the confidentiality, integrity, and availability of data inside IoT environments. Hashing algorithms have gained prominence as a fundamental tool for enhancing IoT security. This survey reviews the state of the art in cryptographic hashing techniques and their application in securing IoT devices, data, and communication. Furthermore, the efficient management of energy resources is essential to prolong the operational lifespan of IoT devices and reduce their environmental impact. Hashing algorithms are also instrumental in optimizing energy consumption through data compression, encryption, and authentication. This survey explores the latest advancements in energy-efficient IoT systems and how hashing algorithms contribute to energy management strategies. Through a comprehensive analysis of recent research findings and technological advancements, this survey identifies key challenges and open research questions in the fields of IoT security and energy management based on hashing algorithms. It provides valuable insights for researchers, practitioners, and policymakers to further advance the state of the art in these critical IoT domains

FPGA-Based Testbed for Fault Injection on SHA-256

In real world applications, cryptographic algorithms are implemented in hardware or software on specific devices. An active attacker may inject faults during the computation process and careful analysis of faulty results can potentially leak secret information. These kinds of attacks known as fault injection attacks may have devastating effects in the field of hardware and embedded cryptography. This research proposes a partial implementation of SHA-256 along with an onboard fault injection circuit implemented on an FPGA. The proposed fault injection circuit is used to generate glitches in the clock to induce a setup time violation in the circuit and thereby produce error(s) in the output. The main objective of this research is to study the viability of fault injection using the clock glitches on the SHA-256