Area-throughput trade-offs for SHA-1 and SHA-256 hash functions’ pipelined designs

High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided. Read More: https://www.worldscientific.com/doi/abs/10.1142/S021812661650032

Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII

As a result of extensive analyses on cryptographic hash functions, NIST started an open competition for selecting a new standard hash function SHA-3. One important aspect of this competition is in evaluating hardware implementations and in collecting much attention of researchers in this area. For a fair comparison of the hardware performance, we propose an evaluation platform, a hardware design strategy, and evaluation criteria that must be consistent for all SHA-3 candidates. First, we define specifications of interface for the SASEBO-GII platform that are suitable for evaluating the performance in real-life hash applications, while one can also evaluate the performance of the SHA-3 core function that has an ideal interface. Second, we discuss the design strategy for high-throughput hardware implementations. Lastly, we explain the evaluation criteria to compare the cost and speed performance of eight SHA-3 candidates out of fourteen

Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.pdf

Recent cryptanalysis on SHA-1 family has led the NIST to call for a public competition named SHA-3 Contest. Efficient implementations on various platforms are a criterion for ranking performance of all the candidates in this competition. It appears that most of the hardware architectures proposed for SHA-3 candidates are basic. In this paper, we focus on an optimized implementation of the Shabal candidate. We improve the state-of-the-art using the unfolding method. This transformation leads to unroll a part of the Shabal core. More precisely, our design can produce a throughput over 3 Gbps on Virtex-5 FPGAs, with a reasonable area usage

Simulation-Based Power Estimation for High Throughput SHA-256 Design on Unfolding Transformation

In recent years, security has grown in importance as a research topic. Several cryptographic SHA-256 hash algorithms have been developed to enhance the performance of data-protection techniques. In security system designs where data transmission must be properly encrypted to avoid eavesdropping and unwanted monitoring, the Hash Function is vital. In constructing the SHA-256 algorithm, high speed, compact size, and low power consumption are all factors to be taken into account for an efficient implementation. The purpose of this project is to reduce dynamic thermal power dissipation of SHA-256 unfolding transformation. State encoding is a method used in reducing power design strategies that have been proposed to lower the dynamic power dissipation of the algorithm. The algorithms are successfully designed using the Altera Quartus II platform. The ModelSim is used to test how accurate the results of simulations written in Verilog code are and to validate them. This study presents the unfolding transformation with Gray encoding approach to reduce the SHA-256 design's power consumption and increase its throughput. The SHA-256 unfolding transformation reduces the amount of clock cycles required for conventional architecture. In this research, the dynamic power SHA-256 unfolding factor 4 with Gray encoding reduces by 43.4 percent from Binary encoding with high throughput of the design. Therefore, it was suggested that to provide high performance of the embedded security system design, an unfolding transformation with Gray encoding design can be applied to the hash function design. Thus, the performance of the SHA-256 design can be greatly enhanced by changing the state encoding with the high number of unfolding factors. Based on this technology, the Power Analyzer in Altera Quartus II may produce an accurate simulation-based power assessment

Technological Evolution from RIS to Holographic MIMO

Multiple-input multiple-output (MIMO) techniques have been widely applied in current cellular networks. To meet the ever-increasing demands on spectral efficiency and network throughput, more and more antennas are equipped at the base station, forming the well-known concept of massive MIMO. However, traditional design with fully digital precoding architecture brings high power consumption and capital expenditure. Cost- and power-efficient solutions are being intensively investigated to address these issues. Among them, both reconfigurable intelligent surface (RIS) and holographic MIMO (HMIMO) stand out. In this chapter, we will focus on the ongoing paradigm shift from RIS to HMIMO, covering both topics in detail. A wide range of closely related topics, e.g., use cases, hardware architectures, channel modeling and estimation, RIS beamforming, HMIMO beamforming, performance analyses of spectral- and energy-efficiency, and challenges and outlook, will be covered to show their potential to be applied in the next-generation wireless networks as well as the rationales for the technological evolution from RIS to holographic MIMO

Construction and functional validation of combinatorial designed ankyrin repeat protein (DARPin) libraries for phage display

Designed ankyrin repeat protein (DARPin) is one of the most advanced alternative scaffold proteins. In this study, a combinatorial DARPin library for phage display was constructed. Firstly, a binary DARPin phage display library (termed BiLiBST) was constructed containing variating tyrosine and serine residues. Five PelB signal sequence mutants were then analyzed to find the one with the best display levels for BiLiBST. These variants were found in earlier study on anti-GFP DARPin display using modified signal sequence, but it was not known if the increased display levels were a generic behavior irrespective of displaying either fixed DARPin protein or library DARPin. The capability of each PelB variant to display BiLiBST was determined by anti-DARPin immunoassay, and the phage stocks titers were normalized by total phage immunoassay. All tested PelB variants exhibited statistically significant improvement in display of the BiLiBST compared to the parental PelB and few variants had even twofold higher display efficiency than DsbA, which has previously been the standard for filamentous phage display of DARPins. The BiLiBST library was displayed with DN5 signal sequence and preselected for open reading frames by panning two rounds against anti-DARPin Fabs. The DARPin libraries were effectively purified from frameshifts as the frequency of frameshift decreased from 50 % to 13 %. The main DARPin library construction was performed by assembly PCR using purified BiLiBST as template and its validity was confirmed by selecting against the GST-tagged protein N from SARS-COV-2 for three rounds. Successful enrichment of binders was confirmed by phage immunoreactivity assay with signal to background ratios up to 11-fold. This is a solid foundation for further molecular diversification and library construction

Proceedings of the first international workshop on Investigating dataflow in embedded computing architectures (IDEA 2015), January 21, 2015, Amsterdam, The Netherlands

IDEA '15 held at HiPEAC 2015, Amsterdam, The Netherlands on January 21st, 2015 is the rst workshop on Investigating Data ow in Embedded computing Architectures. This technical report comprises of the proceedings of IDEA '15. Over the years, data ow has been gaining popularity among Embedded Systems researchers around Europe and the world. However, research on data ow is limited to small pockets in dierent communities without a common forum for discussion. The goal of the workshop was to provide a platform to researchers and practitioners to present work on modelling and analysis of present and future high performance embedded computing architectures using data ow. Despite being the rst edition of the workshop, it was very pleasant to see a total of 14 submissions, out of which 6 papers were selected following a thorough reviewing process. All the papers were reviewed by at least 5 reviewers. This workshop could not have become a reality without the help of a Technical Program Committee (TPC). The TPC members not only did the hard work to give helpful reviews in time, but also participated in extensive discussion following the reviewing process, leading to an excellent workshop program and very valuable feedback to authors. Likewise, the Organisation Committee also deserves acknowledgment to make this workshop a successful event. We take this opportunity to thank everyone who contributed in making this workshop a success