3 research outputs found
Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS
Continuous scaling of CMOS has been the major catalyst in miniaturization of
integrated circuits (ICs) and crucial for global socio-economic progress.
However, scaling to sub-20nm technologies is proving to be challenging as
MOSFETs are reaching their fundamental limits and interconnection bottleneck is
dominating IC operational power and performance. Migrating to 3-D, as a way to
advance scaling, has eluded us due to inherent customization and manufacturing
requirements in CMOS that are incompatible with 3-D organization. Partial
attempts with die-die and layer-layer stacking have their own limitations. We
propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift
in technology scaling as well as design. We co-architect Skybridge's core
aspects, from device to circuit style, connectivity, thermal management, and
manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D
template. Our extensive bottom-up simulations, accounting for detailed material
system structures, manufacturing process, device, and circuit parasitics,
carried through for several designs including a designed microprocessor, reveal
a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in
interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction
features are shown to successfully manage IC thermal profiles in 3-D. Skybridge
can provide continuous scaling of integrated circuits beyond CMOS in the 21st
century.Comment: 53 Page
Interconnects architectures for many-core era using surface-wave communication
PhD ThesisNetworks-on-chip (NoCs) is a communication paradigm that has
emerged aiming to address on-chip communication challenges and
to satisfy interconnection demands for chip-multiprocessors (CMPs).
Nonetheless, there is continuous demand for even higher computational
power, which is leading to a relentless downscaling of CMOS
technology to enable the integration of many-cores. However, technology
downscaling is in favour of the gate nodes over wires in terms
of latency and power consumption. Consequently, this has led to the
era of many-core processors where power consumption and performance
are governed by inter-core communications rather than core
computation. Therefore, NoCs need to evolve from being merely metalbased
implementations which threaten to be a performance and power
bottleneck for many-core efficiency and scalability.
To overcome such intensified inter-core communication challenges,
this thesis proposes a novel interconnect technology: the surface-wave
interconnect (SWI). This new RF-based on-chip interconnect has notable
characteristics compared to cutting-edge on-chip interconnects
in terms of CMOS compatibility, high speed signal propagation, low
power dissipation, and massive signal fan-out. Nonetheless, the realization
of the SWI requires investigations at different levels of abstraction,
such as the device integration and RF engineering levels. The aim
of this thesis is to address the networking and system level challenges
and highlight the potential of this interconnect. This should
encourage further research at other levels of abstraction. Two specific
system-level challenges crucial in future many-core systems are tackled
in this study, which are cross-the-chip global communication and
one-to-many communication.
This thesis makes four major contributions towards this aim. The
first is reducing the NoC average-hop count, which would otherwise
increase packet-latency exponentially, by proposing a novel hybrid
interconnect architecture. This hybrid architecture can not only utilize
both regular metal-wire and SWI, but also exploits merits of
both bus and NoC architectures in terms of connectivity compared to
other general-purpose on-chip interconnect architectures. The second
contribution addresses global communication issues by developing
a distance-based weighted-round-robin arbitration (DWA) algorithm.
This technique prioritizes global communication to be send via SWI
short-cuts, which offer more efficient power dissipation and faster
across-the-chip signal propagation. Results obtained using a cycleaccurate
simulator demonstrate the effectiveness of the proposed
system architecture in terms of significant power reduction, considervii
able average delay reduction and higher throughput compared to a
regular NoC. The third contribution is in handling multicast communications,
which are normally associated with traffic overload, hotspots
and deadlocks and therefore increase, by an order of magnitude the
power consumption and latency. This has been achieved by proposing
a novel routing and centralized arbitration schemes that exploits
the SWI0s remarkable fan-out features. The evaluation demonstrates
drastic improvements in the effectiveness of the proposed architecture
in terms of power consumption ( 2-10x) and performance ( 22x) but
with negligible hardware overheads ( 2%). The fourth contribution is
to further explore multicast contention handling in a flexible decentralized
manner, where original techniques such as stretch-multicast
and ID-tagging flow control have been developed. A comparison of
these techniques shows that the decentralized approach is superior
to the centralized approach with low traffic loads, while the latter
outperforms the former near and after NoC saturation
Development of a Waveform Sampling ASIC with Femtosecond Timing for a Low Occupancy Vertex Detector.
Ph.D. Thesis. University of Hawaiʻi at Mānoa 2018