1,308 research outputs found
Optimal discrimination between transient and permanent faults
An important practical problem in fault diagnosis is discriminating between permanent faults and transient faults. In many computer systems, the majority of errors are due to transient faults. Many heuristic methods have been used for discriminating between transient and permanent faults; however, we have found no previous work stating this decision problem in clear probabilistic terms. We present an optimal procedure for discriminating between transient and permanent faults, based on applying Bayesian inference to the observed events (correct and erroneous results). We describe how the assessed probability that a module is permanently faulty must vary with observed symptoms. We describe and demonstrate our proposed method on a simple application problem, building the appropriate equations and showing numerical examples. The method can be implemented as a run-time diagnosis algorithm at little computational cost; it can also be used to evaluate any heuristic diagnostic procedure by compariso
The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs
The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-642-38789-0_7Current integration scales are increasing the number and types of faults that embedded systems must face. Traditional approaches focus on dealing with those transient and permanent faults that impact the state or output of systems, whereas little research has targeted those faults being logically, electrically or temporally masked -which we have named fugacious. A fast detection and precise diagnosis of faults occurrence, even if the provided service is unaffected, could be of invaluable help to determine, for instance, that systems are currently under the influence of environmental disturbances like radiation, suffering from wear-out, or being affected by an intermittent fault. Upon detection, systems may react to adapt the deployed fault tolerance mechanisms to the diagnosed problem. This paper explores these ideas evaluating challenges and requirements involved, and provides an outline of potential techniques to be applied.This work has been funded by Spanish Ministry of Economy ARENES project (TIN2012-38308-C02-01)Espinosa García, J.; Andrés Martínez, DD.; Ruiz, JC.; Gil, P. (2013). The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs. En Dependable Computing. Springer. 76-87. https://doi.org/10.1007/978-3-642-38789-0_7S7687Narayanan, V., Xie, Y.: Reliability concerns in embedded systems design. IEEE Computer 1(39), 118–120 (2006)Hannius, O., Karlsson, J.: Impact of soft errors in a jet engine controller. In: Ortmeier, F., Daniel, P. (eds.) SAFECOMP 2012. LNCS, vol. 7612, pp. 223–234. Springer, Heidelberg (2012)Borkar, S.: Designing reliable systems from unreliable components: the challenges of transistor variability and degradation. IEEE Micro 25(6), 10–16 (2005)JEDEC: Measurement and reporting of alpha particle and terrestrial cosmic ray-induced soft errors in semiconductor devices. JEDEC Standard JESD89A. JEDEC (2006)Gracia-Moran, J., Gil-Tomas, D., Saiz-Adalid, L.J., Baraza, J.C., Gil-Vicente, P.J.: Experimental validation of a fault tolerant microcomputer system against intermittent faults. In: DSN, pp. 413–418 (2010)Constantinescu, C.: Intermittent faults and effects on reliability of integrated circuits. In: Proceedings of the 2008 Annual Reliability and Maintainability Symposium, pp. 370–374. IEEE Computer Society, Washington, DC (2008)Avizienis, A., Laprie, J.C., Randell, B., Landwehr, C.: Basic concepts and taxonomy of dependable and secure computing. IEEE Trans. Dependable Secur. Comput. 1, 11–33 (2004)Johnson, C., Holloway, C.: The dangers of failure masking in fault-tolerant software: Aspects of a recent in-flight upset event. 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IEEE Transactions on Nuclear Science 51, 3278–3284 (2004)Nightingale, E.B., Douceur, J.R., Orgovan, V.: Cycles, cells and platters: an empirical analysisof hardware failures on a million consumer pcs. In: Proceedings of the Sixth Conference on Computer Systems, EuroSys 2011, pp. 343–356. ACM, New York (2011)Kimseng, K., Hoit, M., Tiwari, N., Pecht, M.: Physics-of-failure assessment of a cruise control module. Microelectronics Reliability 39(10), 1423–1444 (1999)Savir, J.: Detection of single intermittent faults in sequential circuits. IEEE Trans. Comput. 29(7), 673–678 (1980)Correcher, A., Garcia, E., Morant, F., Quiles, E., Rodriguez, L.: Intermittent failure dynamics characterization. IEEE Transactions on Reliability 61(3), 649–658 (2012)Sorensen, B., Kelly, G., Sajecki, A., Sorensen, P.: An analyzer for detecting intermittent faults in electronic devices. In: AUTOTESTCON 1994. IEEE Systems Readiness Technology Conference. ‘Cost Effective Support Into the Next Century’, Conference Proceedings, pp. 417–421 (September 1994)Sosnowski, J.: Transient fault tolerance in digital systems. IEEE Micro 14(1), 24–35 (1994)Bondavalli, A., Chiaradonna, S., Di Giandomenico, F., Grandoni, F.: Threshold-based mechanisms to discriminate transient from intermittent faults. IEEE Trans. Comput. 49(3), 230–245 (2000)Rashid, L., Pattabiraman, K., Gopalakrishnan, S.: Intermittent hardware errors and recovery: modelling and evaluation. In: International Conference on Quantitative Evaluation of Systems, QEST (2012)Touba, N.A., McCluskey, E.J.: Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. CAD 16(7), 783–789 (1997)Nicolaidis, M., Manich, S., Figueras, J.: Achieving fault secureness in parity prediction arithmetic operators: General conditions and implementations. In: Proceedings of the 1996 European conference on Design and Test, EDTC 1996, pp. 186–193. IEEE Computer Society, Washington, DC (1996)Ko, S.B., Lo, J.C.: Efficient realization of parity prediction functions in fpgas. J. Electron. Test. 20(5), 489–499 (2004)D’Angelo, S., Sechi, G.R., Metra, C.: Transient and permanent fault diagnosis for fpga-based tmr systems. In: Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 1999, pp. 330–338. IEEE Computer Society, Washington, DC (1999)Kim, C.: Detection and location of intermittent faults by monitoring carrier signal channel behavior of electrical interconnection system. In: Electric Ship Technologies Symposium, ESTS 2009, pp. 449–455. IEEE (April 2009
Distributed Fault Detection in Smart Spaces Based on Trust Management
AbstractApplication performance in a smart space is affected by faulty behaviours of nodes and communication networks. Detection of faults helps diagnosis of problems and maintenance can be done to restore performance, for example, by replacing or reconfiguring faulty parts. Fault detection methods in the literature are too complex for typical low-resource devices and they do not perform well in detecting intermittent faults. We propose a fully distributed fault detection method that relies on evaluating statements about trustworthiness of aggregated data from neighbors. Given one or more trust statements that describe a fault-free state, the trustor node determines for each observation coming from the trustee whether it is an outlier or not. Several fault types can be explored using different trust statements whose parameters are assessed differently. The trustor subsequently captures the observation history of the trustee node in only two evidence variables using evidence update rules that give more weight to recent observations. The proposed method detects not only permanent faults but also intermittent faults with high accuracy and low false alarm rate
Environmental stress level evaluation approach based on physical model and interval grey association degree
AbstractAssociating environmental stresses (ESs) with built-in test (BIT) output is an important means to help diagnose intermittent faults (IFs). Aiming at low efficiency in association of traditional time stress measurement device (TSMD), an association model is built. Thereafter, a novel approach is given to evaluate the integrated environmental stress (IES) level. Firstly, the selection principle and approach of main environmental stresses (MESs) and key characteristic parameters (KCPs) are presented based on fault mode, mechanism, and ESs analysis (FMMEA). Secondly, reference stress events (RSEs) are constructed by dividing IES into three stress levels according to its impact on faults; and then the association model between integrated environmental stress event (IESE) and BIT output is built. Thirdly, an interval grey association approach to evaluate IES level is proposed due to the interval number of IES value. Consequently, the association output can be obtained as well. Finally, a case study is presented to demonstrate the proposed approach. Results show the proposed model and approach are effective and feasible. This approach can be used to guide ESs measure, record, and association. It is well suited for on-line assistant diagnosis of faults, especially IFs
Integrated Support for Handoff Management and Context-Awareness in Heterogeneous Wireless Networks
The overwhelming success of mobile devices and wireless
communications is stressing the need for the development of
mobility-aware services. Device mobility requires services
adapting their behavior to sudden context changes and being
aware of handoffs, which introduce unpredictable delays and
intermittent discontinuities. Heterogeneity of wireless
technologies (Wi-Fi, Bluetooth, 3G) complicates the situation,
since a different treatment of context-awareness and handoffs is
required for each solution. This paper presents a middleware
architecture designed to ease mobility-aware service
development. The architecture hides technology-specific
mechanisms and offers a set of facilities for context awareness
and handoff management. The architecture prototype works with
Bluetooth and Wi-Fi, which today represent two of the most
widespread wireless technologies. In addition, the paper discusses
motivations and design details in the challenging context of
mobile multimedia streaming applications
New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs
Tesis por compendio[EN] Relevance of electronics towards safety of common devices has only been growing, as an ever growing stake of the functionality is assigned to them. But of course, this comes along the constant need for higher performances to fulfill such functionality requirements, while keeping power and budget low. In this scenario, industry is struggling to provide a technology which meets all the performance, power and price specifications, at the cost of an increased vulnerability to several types of known faults or the appearance of new ones.
To provide a solution for the new and growing faults in the systems, designers have been using traditional techniques from safety-critical applications, which offer in general suboptimal results. In fact, modern embedded architectures offer the possibility of optimizing the dependability properties by enabling the interaction of hardware, firmware and software levels in the process. However, that point is not yet successfully achieved. Advances in every level towards that direction are much needed if flexible, robust, resilient and cost effective fault tolerance is desired. The work presented here focuses on the hardware level, with the background consideration of a potential integration into a holistic approach.
The efforts in this thesis have focused several issues: (i) to introduce additional fault models as required for adequate representativity of physical effects blooming in modern manufacturing technologies, (ii) to provide tools and methods to efficiently inject both the proposed models and classical ones, (iii) to analyze the optimum method for assessing the robustness of the systems by using extensive fault injection and later correlation with higher level layers in an effort to cut development time and cost, (iv) to provide new detection methodologies to cope with challenges modeled by proposed fault models, (v) to propose mitigation strategies focused towards tackling such new threat scenarios and (vi) to devise an automated methodology for the deployment of many fault tolerance mechanisms in a systematic robust way.
The outcomes of the thesis constitute a suite of tools and methods to help the designer of critical systems in his task to develop robust, validated, and on-time designs tailored to his application.[ES] La relevancia que la electrónica adquiere en la seguridad de los productos ha crecido inexorablemente, puesto que cada vez ésta copa una mayor influencia en la funcionalidad de los mismos. Pero, por supuesto, este hecho viene acompañado de una necesidad constante de mayores prestaciones para cumplir con los requerimientos funcionales, al tiempo que se mantienen los costes y el consumo en unos niveles reducidos. En este escenario, la industria está realizando esfuerzos para proveer una tecnología que cumpla con todas las especificaciones de potencia, consumo y precio, a costa de un incremento en la vulnerabilidad a múltiples tipos de fallos conocidos o la introducción de nuevos.
Para ofrecer una solución a los fallos nuevos y crecientes en los sistemas, los diseñadores han recurrido a técnicas tradicionalmente asociadas a sistemas críticos para la seguridad, que ofrecen en general resultados sub-óptimos. De hecho, las arquitecturas empotradas modernas ofrecen la posibilidad de optimizar las propiedades de confiabilidad al habilitar la interacción de los niveles de hardware, firmware y software en el proceso. No obstante, ese punto no está resulto todavía. Se necesitan avances en todos los niveles en la mencionada dirección para poder alcanzar los objetivos de una tolerancia a fallos flexible, robusta, resiliente y a bajo coste. El trabajo presentado aquí se centra en el nivel de hardware, con la consideración de fondo de una potencial integración en una estrategia holística.
Los esfuerzos de esta tesis se han centrado en los siguientes aspectos: (i) la introducción de modelos de fallo adicionales requeridos para la representación adecuada de efectos físicos surgentes en las tecnologías de manufactura actuales, (ii) la provisión de herramientas y métodos para la inyección eficiente de los modelos propuestos y de los clásicos, (iii) el análisis del método óptimo para estudiar la robustez de sistemas mediante el uso de inyección de fallos extensiva, y la posterior correlación con capas de más alto nivel en un esfuerzo por recortar el tiempo y coste de desarrollo, (iv) la provisión de nuevos métodos de detección para cubrir los retos planteados por los modelos de fallo propuestos, (v) la propuesta de estrategias de mitigación enfocadas hacia el tratamiento de dichos escenarios de amenaza y (vi) la introducción de una metodología automatizada de despliegue de diversos mecanismos de tolerancia a fallos de forma robusta y sistemática.
Los resultados de la presente tesis constituyen un conjunto de herramientas y métodos para ayudar al diseñador de sistemas críticos en su tarea de desarrollo de diseños robustos, validados y en tiempo adaptados a su aplicación.[CA] La rellevància que l'electrònica adquireix en la seguretat dels productes ha crescut inexorablement, puix cada volta més aquesta abasta una major influència en la funcionalitat dels mateixos. Però, per descomptat, aquest fet ve acompanyat d'un constant necessitat de majors prestacions per acomplir els requeriments funcionals, mentre es mantenen els costos i consums en uns nivells reduïts. Donat aquest escenari, la indústria està fent esforços per proveir una tecnologia que complisca amb totes les especificacions de potència, consum i preu, tot a costa d'un increment en la vulnerabilitat a diversos tipus de fallades conegudes, i a la introducció de nous tipus.
Per oferir una solució a les noves i creixents fallades als sistemes, els dissenyadors han recorregut a tècniques tradicionalment associades a sistemes crítics per a la seguretat, que en general oferixen resultats sub-òptims. De fet, les arquitectures empotrades modernes oferixen la possibilitat d'optimitzar les propietats de confiabilitat en habilitar la interacció dels nivells de hardware, firmware i software en el procés. Tot i això eixe punt no està resolt encara. Es necessiten avanços a tots els nivells en l'esmentada direcció per poder assolir els objectius d'una tolerància a fallades flexible, robusta, resilient i a baix cost. El treball ací presentat se centra en el nivell de hardware, amb la consideració de fons d'una potencial integració en una estratègia holística.
Els esforços d'esta tesi s'han centrat en els següents aspectes: (i) la introducció de models de fallada addicionals requerits per a la representació adequada d'efectes físics que apareixen en les tecnologies de fabricació actuals, (ii) la provisió de ferramentes i mètodes per a la injecció eficient del models proposats i dels clàssics, (iii) l'anàlisi del mètode òptim per estudiar la robustesa de sistemes mitjançant l'ús d'injecció de fallades extensiva, i la posterior correlació amb capes de més alt nivell en un esforç per retallar el temps i cost de desenvolupament, (iv) la provisió de nous mètodes de detecció per cobrir els reptes plantejats pels models de fallades proposats, (v) la proposta d'estratègies de mitigació enfocades cap al tractament dels esmentats escenaris d'amenaça i (vi) la introducció d'una metodologia automatitzada de desplegament de diversos mecanismes de tolerància a fallades de forma robusta i sistemàtica.
Els resultats de la present tesi constitueixen un conjunt de ferramentes i mètodes per ajudar el dissenyador de sistemes crítics en la seua tasca de desenvolupament de dissenys robustos, validats i a temps adaptats a la seua aplicació.Espinosa García, J. (2016). New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/73146TESISCompendi
Machine learning methods for fault classification
With the constant evolution and ever-increasing transistor densities in semiconductor technology, error rates are on the rise. Errors that occur on semiconductor chips can be attributed to permanent, transient or intermittent faults. Out of these errors, once permanent errors appear, they do not go away and once intermittent faults appear on chips, the probability that they will occur again is high, making these two types of faults critical. Transient faults occur very rarely, making them non-critical. Incorrect classification during manufacturing tests in case of critical faults, may result in failure of the chip during operational lifetime or decrease in product quality, whereas discarding chips with non-critical faults may result in unnecessary yield loss. Existing mechanisms to distinguish between the fault types are mostly rule-based, and as fault types start manifesting similarly as we move to lower technology nodes, these rules become obsolete over time. Hence, rules need to be updated every time the technology is changed. Machine learning approaches have shown that the uncertainty can be compensated with previous experience. In our case, the ambiguity of classification rules can be compensated by storing past classification decisions and learn from those for accurate classification. This thesis presents an effective solution to the problem of fault classification in VLSI chips using Support Vector Machine (SVM) based machine learning techniques
Fault Diagnosis Algorithms for Wireless Sensor Networks
The sensor nodes in wireless sensor networks (WSNs) are deployed in unattended and hostile environments. The ill-disposed environment affects the monitoring infrastructure that includes the sensor nodes and the links.
In addition, node failures and environmental hazards cause frequent topology change, communication failure, and network partition. This in turn adds a new dimension to the fragility of the WSN topology. Such perturbations are far more common in WSNs than those found in conventional wireless networks. These perturbations demand efficient techniques for discovering disruptive behavior in
WSNs. Traditional fault diagnosis techniques devised for wired interconnected networks, and conventional wireless networks are not directly applicable to WSNs due to its specific requirements and limitations.
System-level diagnosis is a technique to identify faults in distributed networks such as multiprocessor systems, wired interconnected networks, and conventional wireless networks. Recently, this has been applied on ad hoc networks and WSNs. This is performed by deduction, based on information in the form of results of tests applied to the sensor nodes. Neighbor coordination-based system-level diagnosis is a variation of this method, which exploits the spatio-temporal correlation between sensor measurements. In this thesis, we present a new approach to diagnose faulty
sensor nodes in a WSN, which works in conjunction with the underlying clustering protocol and exploits spatio-temporal correlation between sensor measurements. An advantage of this method is that the diagnostic operation constitutes real work performed by the system, rather than a specialized diagnostic task. In this way, the normal operation of the network can be used for the diagnosis and resulting less time and message overhead. In this thesis, we have devised and evaluated fault diagnosis algorithms for WSNs considering persistence of the faults (transient,
intermittent, and permanent), faults in communication channels and in one of the approaches, we attempt to solve the issue of node mobility in diagnosis.
A cluster based distributed fault diagnosis (CDFD) algorithm is proposed where the diagnostic local view is obtained by exploiting the spatially correlated sensor measurements. We derived an optimal threshold for effective fault diagnosis in sparse networks. The message complexity of CDFD is O(n) and the number of bits exchanged to diagnose the network are O(n log2 n). The intermittent fault diagnosis is formulated as a multiobjective optimization problem based on the inter-test interval and number of test repetitions required to diagnose the intermittent faults. The two objectives such as detection latency and energy overhead are taken into consideration with a constraint of detection errors. A high level (> 95%) of detection accuracy is achieved while keeping the false alarm rate low (< 1%) for sparse networks. The proposed cluster based distributed intermittent fault diagnosis (CDIFD) algorithm is energy efficient because in CDIFD, diagnostic messages are sent as the output of the routine
tasks of the WSNs. A count and threshold-based mechanism is used to discriminate the persistence of faults. The main characteristics of these faults are the amounts of time the fault disappears. We adopt this state-holding time to discriminate transient from intermittent or permanent faults. The proposed cluster based distributed fault
diagnosis and discrimination (CDFDD) algorithm is energy efficient due to the improved network lifetime which is greater than 1150 data-gathering rounds with transient fault rates as high as 20%.
A mobility aware hierarchal architecture is proposed which is to detect hard and soft faults in dynamic WSN topology assuming random movements of nodes in the WSN. A test pattern that ensures error checking of each functional block of a sensor node is employed to diagnose the network. The proposed mobility aware cluster based distributed fault diagnosis (MCDFD) algorithm assures a better packet delivery ratio (> 80%) in highly dynamic networks with a fault rate as high as 30%. The network lifetime is more than 900 data-gathering rounds in a highly dynamic network with a fault rate as high as 20%
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