Using Multi-Threshold Threshold Gates in RTD-based Logic Design. A Case Study

The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, threshold gates can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing Multi-Threshold Threshold Gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of latency, device counts and power consumption.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Digital IP Protection Using Threshold Voltage Control

This paper proposes a method to completely hide the functionality of a digital standard cell. This is accomplished by a differential threshold logic gate (TLG). A TLG with $n$ inputs implements a subset of Boolean functions of $n$ variables that are linear threshold functions. The output of such a gate is one if and only if an integer weighted linear arithmetic sum of the inputs equals or exceeds a given integer threshold. We present a novel architecture of a TLG that not only allows a single TLG to implement a large number of complex logic functions, which would require multiple levels of logic when implemented using conventional logic primitives, but also allows the selection of that subset of functions by assignment of the transistor threshold voltages to the input transistors. To obfuscate the functionality of the TLG, weights of some inputs are set to zero by setting their device threshold to be a high $V_t$. The threshold voltage of the remaining transistors is set to low $V_t$ to increase their transconductance. The function of a TLG is not determined by the cell itself but rather the signals that are connected to its inputs. This makes it possible to hide the support set of the function by essentially removing some variable from the support set of the function by selective assignment of high and low $V_t$ to the input transistors. We describe how a standard cell library of TLGs can be mixed with conventional standard cells to realize complex logic circuits, whose function can never be discovered by reverse engineering. A 32-bit Wallace tree multiplier and a 28-bit 4-tap filter were synthesized on an ST 65nm process, placed and routed, then simulated including extracted parastics with and without obfuscation. Both obfuscated designs had much lower area (25%) and much lower dynamic power (30%) than their nonobfuscated CMOS counterparts, operating at the same frequency

Memristor Threshold Logic FFT Circuits

One of the possible approaches to achieve more than Moore\u27s law with signal processing circuits is to inspire from functioning of human brain to mimic neural functions by exploring emerging technologies such as memristor circuits. While fast Fourier transform (FFT) implementations are largely based on CMOS gates, they are limited by the computation speed and availability limits on the number of Boolean variables it can handle at a given time. Biological neurons and networks on the other hand are generalized in nature and can handle both analogue and digital signals. Through this chapter, memristor‐based resistive threshold logic family of gates that inspire from brain‐like large variable logic functions is introduced. This logic consists of a memristors acting as weights to the inputs followed by threshold operations emulating neuronal synapse. Using this Boolean logic, a processing unit that can compute Fourier transform of a given set of inputs was developed. Various comparisons of the circuit are found to be advantageous in implementing neuromorphic circuits. The existing logic families were carried out and the proposed logic family was found too advantageous in many ways

Boolean Functions: Theory, Algorithms, and Applications

This monograph provides the first comprehensive presentation of the theoretical, algorithmic and applied aspects of Boolean functions, i.e., {0,1}-valued functions of a finite number of {0,1}-valued variables. The book focuses on algebraic representations of Boolean functions, especially normal form representations. It presents the fundamental elements of the theory (Boolean equations and satisfiability problems, prime implicants and associated representations, dualization, etc.), an in-depth study of special classes of Boolean functions (quadratic, Horn, shellable, regular, threshold, read-once, etc.), and two fruitful generalizations of the concept of Boolean functions (partially defined and pseudo-Boolean functions). It features a rich bibliography of about one thousand items. Prominent among the disciplines in which Boolean methods play a significant role are propositional logic, combinatorics, graph and hypergraph theory, complexity theory, integer programming, combinatorial optimization, game theory, reliability theory, electrical and computer engineering, artificial intelligence, etc. The book contains applications of Boolean functions in all these areas

On reliable computation over larger alphabets

We present two new positive results for reliable computation using formulas over physical alphabets of size $q > 2$. First, we show that for logical alphabets of size $\ell = q$ the threshold for denoising using gates subject to $q$-ary symmetric noise with error probability $\epsilon$ is strictly larger that possible for Boolean computation and we demonstrate a clone of $q$-ary functions that can be reliably computed up to this threshold. Secondly, we provide an example where $\ell < q$, showing that reliable Boolean computation can be performed using $2$-input ternary logic gates subject to symmetric ternary noise of strength $\epsilon < 1/6$ by using the additional alphabet element for error signalling.Comment: 14 pages, 2 figure