822 research outputs found

    MIDAS: Automated Approach to Design Microwave Integrated Inductors and Transformers on Silicon

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    The design of modern radiofrequency integrated circuits on silicon operating at microwave and millimeter-waves requires the integration of several spiral inductors and transformers that are not commonly available in the process design-kits of the technologies. In this work we present an auxiliary CAD tool for Microwave Inductor (and transformer) Design Automation on Silicon (MIDAS) that exploits commercial simulators and allows the implementation of an automatic design flow, including three-dimensional layout editing and electromagnetic simulations. In detail, MIDAS allows the designer to derive a preliminary sizing of the inductor (transformer) on the bases of the design entries (specifications). It draws the inductor (transformer) layers for the specific process design kit, including vias and underpasses, with or without patterned ground shield, and launches the electromagnetic simulations, achieving effective design automation with respect to the traditional design flow for RFICs. With the present software suite the complete design time is reduced significantly (typically 1 hour on a PC based on Intel® Pentium® Dual 1.80GHz CPU with 2-GB RAM). Afterwards both the device equivalent circuit and the layout are ready to be imported in the Cadence environment

    Cryogenic silicon surface ion trap

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    Trapped ions are pre-eminent candidates for building quantum information processors and quantum simulators. They have been used to demonstrate quantum gates and algorithms, quantum error correction, and basic quantum simulations. However, to realise the full potential of such systems and make scalable trapped-ion quantum computing a reality, there exist a number of practical problems which must be solved. These include tackling the observed high ion-heating rates and creating scalable trap structures which can be simply and reliably produced. Here, we report on cryogenically operated silicon ion traps which can be rapidly and easily fabricated using standard semiconductor technologies. Single 40^{40}Ca+^+ ions have been trapped and used to characterize the trap operation. Long ion lifetimes were observed with the traps exhibiting heating rates as low as nˉ˙=\dot{\bar{n}}= 0.33 phonons/s at an ion-electrode distance of 230 μ\mum. These results open many new avenues to arrays of micro-fabricated ion traps.Comment: 12 pages, 4 figures, 1 tabl

    Mask Programmable CMOS Transistor Arrays for Wideband RF Integrated Circuits

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    A mask programmable technology to implement RF and microwave integrated circuits using an array of standard 90-nm CMOS transistors is presented. Using this technology, three wideband amplifiers with more than 15-dB forward transmission gain operating in different frequency bands inside a 4-22-GHz range are implemented. The amplifiers achieve high gain-bandwidth products (79-96 GHz) despite their standard multistage designs. These amplifiers are based on an identical transistor array interconnected with application specific coplanar waveguide (CPW) transmission lines and on-chip capacitors and resistors. CPW lines are implemented using a one-metal-layer post-processing technology over a thick Parylene-N (15 mum ) dielectric layer that enables very low loss lines (~0.6 dB/mm at 20 GHz) and high-performance CMOS amplifiers. The proposed integration approach has the potential for implementing cost-efficient and high-performance RF and microwave circuits with a short turnaround time

    Green on-chip inductors in three-dimensional integrated circuits

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    This thesis focuses on the technique for the improvement of quality factor and inductance of the TSV inductors and then on the utilization of TSV inductors in various on-chip applications such as DC-DC converter and resonant clocking. Through-silicon-vias (TSVs) are the enabling technique for three-dimensional integrated circuits (3D ICs). However, their large area significantly reduces the benefits that can be obtained by 3D ICs. On the other hand, a major limiting factor for the implementation of many on-chip circuits such as DC-DC converters and resonant clocking is the large area overhead induced by spiral inductors. Several works have been proposed in the literature to make inductors out of idle TSVs. In this thesis, the technique to improve the quality factor and inductance is proposed and then discusses about two applications utilizing TSV inductors i.e., inductive DC-DC converters and LC resonant clocking. The TSV inductor performs inferior to spiral inductors due to its increases losses. Hence to improve the performance of the TSV inductor, the losses should be reduced. Inductive DC-DC converters become prominent for on-chip voltage conversion because of their high efficiency compared with other types of converters (e.g. linear and capacitive converters). On the other hand, to reduce on-chip power, LC resonant clocking has become an attractive option due to its same amplitude and phases compared to other resonant clocking methods such as standing wave and rotary wave. A major challenge for both applications is associated with the required inductor area. In this thesis, the effectiveness of such TSV inductors in addressing both challenges are demonstrated --Abstract, page iv

    Trough-silicon-via inductor: Is it real or just a fantasy?

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    Through-silicon-vias (TSVs) can potentially be used to implement inductors in three-dimensional (3D) integrated system for minimal footprint and large inductance. However, different from conventional 2D spiral inductor, TSV inductors are buried in lossy substrate, thus suffering from low quality factors. This thesis presents how various process and design parameters affect their performance. A few interesting phenomena that are unique to TSV inductors are observed. We then proposed a novel shield mechanism utilizing the micro-channel, a technique conventionally used for heat removal, to reduce the substrate loss. The technique increases the quality factor and inductance of the TSV inductor by up to 21x and 17x respectively. It enables us to implement TSV inductors of up to 38x smaller area and 33% higher quality factor, compared with spiral inductors of the same inductance. To the best of the authors\u27 knowledge, this is the very first in-depth study on TSV inductors. We hope our study shall point out a new and exciting research direction for 3D IC designers --Abstract, page iii

    Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

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    High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to singlecrystalline silicon.Philips Semiconductors and Philips Research in the context of the Philips Associate Centre at DIMES (PACD); Fundação para a Ciência e Tecnologia (FCT) (SFRH/BD/4717/2001, POCTI/ESE/38468/2001, FEDER), and the EC (project Blue Whale IST-2000-10036)

    Three-dimensional micromachined on-chip inductors for high frequency applications

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    Demands for wireless communication are ever-escalating for consumer and military communication applications. The requirements of portability, more functionality and lower cost have been driving forces toward smaller, more sophisticated and flexible wireless devices with lower power consumption. To meet these requirements, monolithically integrated passive inductors with high Q-factors and high self-resonant frequencies are desirable. Q-factor and self-resonant frequency of an inductor are significantly degraded at high frequencies due to conductor ohmic loss, magnetically induced eddy current in the conductive substrate, and lower self-resonant frequency from capacitance between conductive substrate and conductors. In this dissertation, novel three-dimensional arch-like solenoid and dome-shaped spiral inductors are designed, fabricated, and characterized. MEMS-based fabrication techniques such as copper electroplating through voids in thick SU-8 photoresist molds and EAGLE2100 conformal photoresist molds on sacrificial arch-like or dome-shape SJR5740 photoresist mounds are utilized. An air gap between the inductor and the silicon substrate is used to reduce the degradations of inductor performance. According to the Sonnet electromagnetic simulations, 30 μm air-gap suspension over the substrate is an adequate choice for these inductors. Suspended arch-like solenoid copper inductor has flat bottom conductor connected to arch-like top conductor with an air core in between. This design has only 2 contact points per inductor turn to minimize series resistance. Suspended domeshaped spiral copper inductor is fabricated on a sacrificial photoresist dome with the outer end connected to one probe pad, and the inner end connected to the other probe pad through vias and an air-bridge. The sidewalls of spiral turns in this design overlap less with each other thereby reducing inter-turn capacitances. Fabricated inductors are characterized and modeled at high frequencies from Sparameter measurements. ABCD-parameters, derived from the S-parameters are translated into a simplified physical π-model. The resulting arch-like suspended inductors with 2-5 turns have inductances between 0.62 to 0.79 nH, peak Q-factor values between 15.42 to 17 at peak-Q frequencies between 4.7 GHz to 7.0 GHz, and self-resonant frequencies between 47.6 GHz to 88.6 GHz. The 3-turn dome-shaped spiral inductor has inductance of 3.37 nH, peak Q-factor of 35.9 at 1.65 GHz, and self-resonant frequency at 18.74 GHz
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