A Manufacturer Design Kit for Multi-Chip Power Module Layout Synthesis

The development of Multi-Chip Power Modules (MCPMs) has been a key factor in recent advancements in power electronics technologies. MCPMs achieve higher power density by combining multiple power semiconductor devices into one package. The work detailed in this thesis is part of an ongoing project to develop a computer-aided design software tool known as PowerSynth for MCPM layout synthesis and optimization. This thesis focuses on the definition and design of a Manufacturer Design Kit (MDK) for PowerSynth, which enables the designer to design an MCPM for a manufacturer’s fabrication process. The MDK is comprised of a layer stack and technology library, design rule checking (DRC), and layout versus schematic checking. File formats have been defined for layer stack and design rule input, and import functions have been written and integrated with the existing user interface and data structures to allow PowerSynth to accept these file formats as a form of input. Finally, an exhaustive DRC function has been implemented to allow the designer to verify that a synthesized layout meets all design rules before committing the design to manufacturing. This function was validated by running DRC on an example layout solution using two different sets of design rules

Hierarchical quantum classifiers

Quantum circuits with hierarchical structure have been used to perform binary classification of classical data encoded in a quantum state. We demonstrate that more expressive circuits in the same family achieve better accuracy and can be used to classify highly entangled quantum states, for which there is no known efficient classical method. We compare performance for several different parameterizations on two classical machine learning datasets, Iris and MNIST, and on a synthetic dataset of quantum states. Finally, we demonstrate that performance is robust to noise and deploy an Iris dataset classifier on the ibmqx4 quantum computer

Universal Quantum Computation with the Exchange Interaction

Experimental implementations of quantum computer architectures are now being investigated in many different physical settings. The full set of requirements that must be met to make quantum computing a reality in the laboratory [1] is daunting, involving capabilities well beyond the present state of the art. In this report we develop a significant simplification of these requirements that can be applied in many recent solid-state approaches, using quantum dots [2], and using donor-atom nuclear spins [3] or electron spins [4]. In these approaches, the basic two-qubit quantum gate is generated by a tunable Heisenberg interaction (the Hamiltonian is $H_{ij}=J(t){\vec S}_i\cdot{\vec S}_j$ between spins $i$ and $j$), while the one-qubit gates require the control of a local Zeeman field. Compared to the Heisenberg operation, the one-qubit operations are significantly slower and require substantially greater materials and device complexity, which may also contribute to increasing the decoherence rate. Here we introduce an explicit scheme in which the Heisenberg interaction alone suffices to exactly implement any quantum computer circuit, at a price of a factor of three in additional qubits and about a factor of ten in additional two-qubit operations. Even at this cost, the ability to eliminate the complexity of one-qubit operations should accelerate progress towards these solid-state implementations of quantum computation.Comment: revtex, 2 figures, this version appeared in Natur

Benchmarking integrated photonic architectures

Photonic platforms represent a promising technology for the realization of several quantum communication protocols and for experiments of quantum simulation. Moreover, large-scale integrated interferometers have recently gained a relevant role for restricted models of quantum computing, specifically with Boson Sampling devices. Indeed, various linear optical schemes have been proposed for the implementation of unitary transformations, each one suitable for a specific task. Notwithstanding, so far a comprehensive analysis of the state of the art under broader and realistic conditions is still lacking. In the present work we address this gap, providing in a unified framework a quantitative comparison of the three main photonic architectures, namely the ones with triangular and square designs and the so-called fast transformations. All layouts have been analyzed in presence of losses and imperfect control over the reflectivities and phases of the inner structure. Our results represent a further step ahead towards the implementation of quantum information protocols on large-scale integrated photonic devices.Comment: 10 pages, 6 figures + 2 pages Supplementary Informatio

Upward Three-Dimensional Grid Drawings of Graphs

A \emph{three-dimensional grid drawing} of a graph is a placement of the vertices at distinct points with integer coordinates, such that the straight line segments representing the edges do not cross. Our aim is to produce three-dimensional grid drawings with small bounding box volume. We prove that every $n$-vertex graph with bounded degeneracy has a three-dimensional grid drawing with $O(n^{3/2})$ volume. This is the broadest class of graphs admiting such drawings. A three-dimensional grid drawing of a directed graph is \emph{upward} if every arc points up in the z-direction. We prove that every directed acyclic graph has an upward three-dimensional grid drawing with $(n^3)$ volume, which is tight for the complete dag. The previous best upper bound was $O(n^4)$. Our main result is that every $c$-colourable directed acyclic graph ($c$ constant) has an upward three-dimensional grid drawing with $O(n^2)$ volume. This result matches the bound in the undirected case, and improves the best known bound from $O(n^3)$ for many classes of directed acyclic graphs, including planar, series parallel, and outerplanar