Survey on Combinatorial Register Allocation and Instruction Scheduling

Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the last three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization

Modular HLA RTI services: The GRIDS approach

The Generic Runtime Infrastructure for Distributed Simulation (GRIDS) has been developed to investigate modularity issues in distributed simulation. It could be argued that although the HLA RTI is a widespread solution to distributed simulation, it cannot include all possible services. This paper investigates an approach to extending the distributed simulation services available in the HLA RTI. One example of this is bridging support for HLA/DIS legacy integration. This paper therefore presents GRIDS, how GRIDS can be used to provide modular service support for the HLA RTI, and a case study on legacy integration to demonstrate our approach

SFDL: MVC Applied to Workflow Design

Process management based on workflow systems is a growing trend in collaborative environments. One of the most notorious areas of improvement is that of user interfaces, especially since business process definition languages do not address efficiently the point of contact between workflow engines and human interactions. With that in focus, we propose the MVC pattern design to workflow systems. To accomplish this, we have designed a new dynamic view definition language called SFDL, oriented towards the easy interoperability with the different workflow definition languages, while maintaining enough flexibility to be represented in different formats and being adaptable to several environments. To validate our approach, we have carried out an implementation in a real banking scenario, which has provided continuous feedback and enabled us to refine the proposal. The work is fully based on widely accepted and used web standards (XML, YAML, JSON, Atom and REST). Some guidelines are given to facilitate the adoption of our solution

Enhancing an Embedded Processor Core with a Cryptographic Unit for Performance and Security

We present a set of low-cost architectural enhancements to accelerate the execution of certain arithmetic operations common in cryptographic applications on an extensible embedded processor core. The proposed enhancements are generic in the sense that they can be beneficially applied in almost any RISC processor. We implemented the enhancements in form of a cryptographic unit (CU) that offers the programmer an extended instruction set. The CU features a 128-bit wide register file and datapath, which enables it to process 128-bit words and perform 128-bit loads/stores. We analyze the speed-up factors for some arithmetic operations and public-key cryptographic algorithms obtained through these enhancements. In addition, we evaluate the hardware overhead (i.e. silicon area) of integrating the CU into an embedded RISC processor. Our experimental results show that the proposed architectural enhancements allow for a significant performance gain for both RSA and ECC at the expense of an acceptable increase in silicon area. We also demonstrate that the proposed enhancements facilitate the protection of cryptographic algorithms against certain types of side-channel attacks and present an AES implementation hardened against cache-based attacks as a case study