JTEC Panel report on electronic manufacturing and packaging in Japan

This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Low-Power, High-Bandwidth and Ultra-Small Memory Module Design

The main memory subsystem has become inefficient. The performance gained has come at the expenses of power consumption, capacity, and cost. This dissertation proposes novel module, DRAM, and interconnect architectures in an attempt to alleviate these trends. The proposed architectures utilize low-cost interconnects and packaging innovations to substantially reduce the power, and increase the capacity and bandwidth of the main memory system. This dissertation develops the theory behind a low-cost packaging technology to create an 8-die and 32-die memory module. The 32-die memory module measures less than 2 cm3. This dissertation also proposes a 4 Gb DRAM architecture utilizing 64 data pins to supplement the memory module design. This DRAM architecture is inline with ITRS roadmaps and consumes 50% less power while increasing bandwidth by 100%. The large number of data pins is made possible with the use of a low power capacitive-coupled interconnect. As part of the capacitive-coupled interconnect, this dissertation proposes a receiver circuit designed for the capacitive interface. The designs were fabricated in 0.5 μm and 65 nm CMOS technologies. The 0.5 μm design operated at 200 Mbps, and consumed less than 3 pJ/bit of energy. While the 65 nm design operated at 4 Gbps, and consumed less than 15 fJ/bit

NASA Tech Briefs, December 1999

Topics include: Imaging/Videos/Cameras; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Books and Reports

THE ADVANTAGES OF MODEL 4807A HIGH RESOLUTION ACCELEROMETER

This paper is aimed to inform the advantages of model 4807A accelerometer as device of measurement base on literature review. The model 4807A accelerometer is produced by Measurement Specialties, Inc. It has many advantages such as hermetically sealed and offers an amplified signal output covering ranges from ± 2 g to ± 200 g, and built-in mechanical overload stops for shock protection to 5,000 g. This model accelerometer can be applied in many fields, such as Vibration Isolation, Flight Testing, Trajectory Profiling, Structural Monitoring, and Researches & Development

The NASA SBIR product catalog

The purpose of this catalog is to assist small business firms in making the community aware of products emerging from their efforts in the Small Business Innovation Research (SBIR) program. It contains descriptions of some products that have advanced into Phase 3 and others that are identified as prospective products. Both lists of products in this catalog are based on information supplied by NASA SBIR contractors in responding to an invitation to be represented in this document. Generally, all products suggested by the small firms were included in order to meet the goals of information exchange for SBIR results. Of the 444 SBIR contractors NASA queried, 137 provided information on 219 products. The catalog presents the product information in the technology areas listed in the table of contents. Within each area, the products are listed in alphabetical order by product name and are given identifying numbers. Also included is an alphabetical listing of the companies that have products described. This listing cross-references the product list and provides information on the business activity of each firm. In addition, there are three indexes: one a list of firms by states, one that lists the products according to NASA Centers that managed the SBIR projects, and one that lists the products by the relevant Technical Topics utilized in NASA's annual program solicitation under which each SBIR project was selected

Contributions of DOE Weapons Labs and NIST to Semiconductor Technology

This report examines how NIST and DOE weapons laboratories could contribute to advances in semiconductor technology aimed specifically at civilian applications. Semiconductor technology was chosen as an example of a technology focus for a civilian technology initiative, primarily because the industry had already developed a set of comprehensive technology roadmaps and the federal labs had substantial expertise in the area