Low pressure epitaxial growth, fabrication and characterizion of Ge-on-Si photodiodes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 238-249).In order to facilitate the integration of photonic systems onto an electronic chip, near infrared photodiodes utilizing novel materials such as germanium must be monolithically integrated onto the Si CMOS platform. Such near-infrared photodiodes can be utilized for a plethora of applications such as optoelectronic ADCs, optical interconnects, photonic integrated circuits, and near infrared cameras. In this work, the major focus is on investigating processes utilizing a Low Pressure Chemical Vapor Deposition (LPCVD) Applied Materials Epi CenturaTM system to deposit germanium onto silicon substrates (Ge-on-Si). A growth space is identified to deposit blanket and selective epitaxial 1 to 3 rim-thick Ge-on-Si films via a two-step process. These deposited Ge-on-Si films have a low root-mean-square surface roughness (below 2 nm) and a moderate threading dislocation density (- 107 cm-2) after an annealing process. Utilizing these Ge-on-Si films, vertically illuminated Ge-on-Si pin photodiodes are fabricated in a CMOS compatible process. The best photodiodes fabricated in this work have low dark current values (below 10 mA/cm2), high responsivity (- 0.45 A/W at 1.55 pim wavelengths) and 3-dB frequency response in the gigahertz range.(cont.) Due to the importance of the photodiode reverse bias leakage current for circuit applications, the reverse bias leakage current is investigated and characterized in detail for various Ge-on-Si pin photodiodes. Trap assisted tunneling was found to be the dominant reverse bias leakage mechanism. These Ge-on-Si films show great promise for leveraging the integration of photonic devices onto the Very Large Scale Integration (VLSI) platform, and once there is improved reproducibility in the fabrication process, specifically the passivation of germanium surface states, the promise of these Ge-on-Si films can be fully realized.by Oluwamuyiwa Oluwagbemiga OlubuyidePh.D

The Journal of Microelectronic Research 2005

https://scholarworks.rit.edu/meec_archive/1014/thumbnail.jp

Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Optimization and Modelling of Semiconductor Devices in a 0.35 µm CMOS High Temperature Technology

Die vorliegende Arbeit beschäftigte sich mit der Optimierung und Modellierung von Bauelementen in einer 0,35 μm-CMOS-Technologie, die speziell für den Betrieb in einem erweiterten Temperaturbereich von −40 ℃ bis 250 ℃ vorgesehen ist. Bei dieser Technologie handelt es sich um eine Weiterentwicklung einer 1 μm-Technologie, die in weiten Teilen der Prozessierung modifiziert wurde. Durch die geringe Strukturbreite lassen sich komplexere Schaltungen und eine höhere Packungsdichte realisieren. Die Herstellung erfolgt in einer Dünnfilm-SOI-Technologie, die gegenüber einer üblicherweise verwendeten Bulk-Technologie deutliche Vorteile beim Hochtemperaturbetrieb bietet. Die zahlreichen Veränderungen in der neuen Technologie erforderten zunächst die Anpassung des elektrischen Verhaltens verschiedener Bauelemente an die gesetzten Spezifikationen. Dazu gehörte die Charakterisierung und die Parameterextraktion des verkleinerten Transistortyps. Die Optimierung des Durchbruchverhaltens einer Diode, die zum Schutz vor Überspannungspulsen eingesetzt wird, konnte durch die Anpassung der Dotierstoffkonzentrationen erreicht werden. Ebenfalls konnte eine Steigerung der Spannungsfestigkeit eines Hochspannungstransistors erzielt werden, indem u. a. der Avalanche-Effekt durch einen besseren Kanalanschluss vermieden wurde. Neben der Optimierung des elektrischen Verhaltens wurde auch das Zuverlässigkeitsverhalten der Bauelemente verbessert. Hierzu gehörte die Optimierung der Oxidqualität, welche durch Getterung von Kontaminationsatomen signifikant gesteigert werden konnte. Weiterhin konnte auch das Zuverlässigkeitsverhalten der Speicherzellen (EEPROM), welches durch die beiden Aspekte der Datenwechselstabilität und des Datenerhalts beschrieben wird, durch geometrische Veränderungen und Abschirmung der Zelle verbessert werden. Ein weiterer wichtiger Aspekt dieser Arbeit war die Entwicklung von Simulationsmodellen bestimmter Bauelemente in einem breiten Temperaturbereich. Zum einen konnte das elektrische Verhalten von Dioden bei Temperaturen zwischen −40 ℃ und 300 ℃ durch ein Makromodell genau nachgebildet werden. Zum anderen konnten die Datenwechselstabilität und der Datenerhalt der Speicherzelle bis zu einer Temperatur von 450 ℃ mithilfe eines Modells korrekt wiedergegeben werden. Die Modelle werden verwendet, um eine Vorhersage über das Verhalten von Bauelementen bei unterschiedlichen Temperaturen zu treffen, dienen als Hilfsmittel zur Optimierung der Bauelemente und sind für die Simulation von Schaltungen notwendig. Weiterhin wurden in der vorliegenden Arbeit neue Bauelemente vorgestellt, die vor allem für den Einsatz in einem breiten Temperaturbereich konzipiert sind. So wurde eine Schutzstruktur vor Überspannungspulsen vorgeschlagen, die bei einer Betriebsspannung von 3,3 V und einer Temperatur bis 250 ℃ eingesetzt werden soll. Dazu wurde entweder der Punch-Through- oder der Floating-Body-Effekt ausgenutzt, um das Bauelement ab einer bestimmten Spannung in den Leitungszustand zu versetzen. Für den Betrieb eines Hochspannungstransistors wurde in dieser Arbeit eine Bauweise vorgeschlagen, die es ermöglicht, die transistorspezifischen Eigenschaften, wie die Schwellenspannung oder den Leckstrom, in Abhängigkeit der Temperatur deutlich zu verbessern. Somit wurden in dieser Arbeit verschiedene kritische Bereiche einer CMOS-Technologie behandelt, die sich beim Hochtemperaturbetrieb ergeben. Dazu wurden Optimierungen im Bezug auf das elektrische Verhalten bzw. die Zuverlässigkeit vorgeschlagen und neue Bauelemente entwickelt, die vor allem für den Betrieb bei hohen Temperaturen ausgelegt sind. Zusätzlich wurden Simulationsmodelle für den erweiterten Temperaturbereich entwickelt, die nicht zuletzt zur Optimierung der Bauelemente beitragen.The present work focuses on the optimization and modeling of devices from a 0.35 μm technology developed for the operation in a wide temperature range from −40 ℃ up to 250 ℃. This technology is a further development of a 1 μm high temperature technology with various modifications in the processing flow. The shrink of the technology node allows to process more complex integrated circuits with a higher device density. For the wide temperature range, a thin film SOI technology is utilized that shows substantial benefits compared to the commonly used bulk technology. The numerous changes in the new technology require adjustment of the electric behavior of different devices to fulfill the specifications. Within the framework of this study one of the tasks was the characterization and the parameter extraction of the downsized transistor type. Further the breakdown behavior of a diode used for ESD protection was optimized by adapting the doping concentration. The breakdown voltage of a high voltage transistor was enhanced by a proper biasing of the channel area. Besides the optimization of the electric behavior the reliability of the devices was improved as well. For this purpose, the oxide quality was optimized by gettering contaminants. Furthermore the reliability of the memory cells (EEPROM) that can be described by the retention and endurance behavior was increased by geometrical optimization and a better isolation of the cell. In addition, simulation models were developed for specific devices to characterize the electric behavior in a wide temperature range. The characteristics of two different diodes at temperatures between −40 ℃ and 300 ℃ were simulated by a macro model. The endurance and retention behavior of a memory cell was also described by a macro model for temperatures up to 450 ℃. The models are used to predict the behavior of the devices at different temperatures, serve as auxiliary tools to optimize the devices and are also used for circuit simulations. Furthermore, new devices are developed in the present work to enable the operation in a wide temperature range. An ESD device is proposed to protect circuits with a low operating voltage of 3.3 V for temperatures up to 250 ℃. For this purpose, the punch through or floating body effect is used to bring the device in a conduction state at a certain trigger voltage. For the operation of high voltage transistor a new design is proposed, which allows to improve the transistor specific properties (for example leakage current or threshold voltage) at high temperatures. In summary, different critical parts of a CMOS technology designed for high temperature applications are investigated in this work. Optimizations with respect to the electric behavior and the reliability are proposed and new devices are developed to improve the performance at high temperatures. Additionally, simulation models are proposed to allow an accurate description of the electrical device behavior in a wide temperature range and which can also be used to optimize the device performance

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Three dimensional integration technology using copper wafer bonding

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 216-219).With 3-D integration, the added vertical component could theoretically increase the device density per footprint ratio of a given chip by n-fold, provide a means of heterogeneous integration of devices fabricated from different technologies, and reduce the global RC delay to a non-factor in circuits by using smarter 3-D CAD tools for optimizing device placement. This thesis work will focus primarily on the development and realization of a viable 3-D flow fabricated within MTL. Specifically, the presentation will attempt on answering these questions in regards to 3-D: 1. What enabling technologies were needed for 3-D to work ? 2. Does it really work ? 3. Will the "3-D heat dissipation problem" prevent it from working ? 4. What applications is it good for ? Referring to the first item, a viable 3-D integration flow has been developed on both the wafer-and-die-level, and the enabling technologies were the following: Low temperature Cu-Cu thermocompression bonding, an aluminum-Cu based temporary laminate structure used stabilizing the handle wafer - SOI wafer bond, and tooling optimization of the die-die bonder setup in TRL.(cont.,) Next, nominal feasibility of the 3-D flow was demonstrated by fabricating a 21-stage and 43-stage CMOS ring oscillators, where each single CMOS inverter / buffer stage was constructed by connecting NMOS-only devices from one substrate with PMOS-only devices from a separate substrate. Proof-of-concept was accomplished when all 92 Cu-Cu bonds, 204 thru-SOI Cu damascene vias, and 56 pairs of MOSFETs communicated simultaneously to produce a 2.75 MHz (43-stage) and 5.5 MHz (21-stage) oscillators, ringing rail-to-rail at 5 V Vdd under proper Vt adjustments on the SOI-PMOS using integrated backgates. Furthermore, to combat the perceived heat dissipation problem in 3-D, this work focused on using the Cu-Cu interlayer bond as heat dissipators, with Cu planes working as flux spreaders and Cu vias as direct heat conduits. Finally, 3-D RF passive integration onto existing chips can be made feasible, under certain device performance trade-offs, by using cobalt magnetic shielding, which offers at least a -10 dB throughout 0-20 GHz, with a max isolation of -24 dB at 13 GHz, at +4 dBm reference input power.by Andy Fan.Ph.D

On-Chip Integrated Functional Near Infra-Red Spectroscopy (fNIRS) Photoreceiver for Portable Brain Imaging

RÉSUMÉ L'imagerie cérébrale fonctionnelle utilisant la Spectroscopie Fonctionnelle Proche-Infrarouge (SFPI) propose un outil portatif et non invasif de surveillance de l'oxygénation du sang. SFPI est une technique de haute résolution temporelle non invasive, sûr, peu intrusive en temps réel et pour l'imagerie cérébrale à long terme. Il permet de détecter des signaux hémodynamiques à la fois rapides et neuronaux ou lents. Outre les avantages importants des systèmes SFPI, ils souffrent encore de quelques inconvénients, notamment d’une faible résolution spatiale, d’un bruit de niveau modérément élevé et d’une grande sensibilité au mouvement. Afin de surmonter les limites des systèmes actuellement disponibles de SFPI non-portables, dans cette thèse, nous en avons introduit une nouvelle de faible puissance, miniaturisée sur une puce photodétecteur frontal destinée à des systèmes de SFPI portables. Elle contient du silicium photodiode à avalanche (SiAPD), un amplificateur de transimpédance (TIA), et « Quench-Reset », circuits mis en oeuvre en utilisant les technologies CMOS standards pour fonctionner dans les deux modes : linéaire et Geiger. Ainsi, elle peut être appliquée pour les deux fNIRS : en onde continue (CW- SFPI) et pour des applications de comptage de photon unique. Plusieurs SiAPDs ont été mises en oeuvre dans de nouvelles structures et formes (rectangulaires, octogonales, double APDs, imbriquées, netted, quadratiques et hexadecagonal) en utilisant différentes techniques de prévention de la dégradation de bord prématurée. Les principales caractéristiques des SiAPDs sont validées et l'impact de chaque paramètre ainsi que les simulateurs de l'appareil (TCAD, COMSOL, etc) ont été étudiés sur la base de la simulation et de mesure des résultats. Proposées SiAPDs techniques d'exposition avec un gain de grande avalanche, tension faible ventilation et une grande efficacité de détection des photons dans plus de faibles taux de comptage sombres. Trois nouveaux produits à haut gain, bande passante (GBW) et à faible bruit TIA sont introduits basés sur le concept de gain distribué, d’amplificateur logarithmique et sur le rejet automatique du bruit pour être appliqué en mode de fonctionnement linéaire. Le TIA proposé offre une faible consommation, un gain de haute transimpédance, une bande passante ajustable et un très faible bruit d'entrée et de sortie. Le nouveau circuit mixte trempe-reset (MQC) et un MQC contrôlable (CMQC) frontaux offrent une faible puissance, une haute vitesse de comptage de photons avec un commandable de temps de hold-off et temps de réinitialiser. La première intégration sur puce de SiAPDs avec TIA et Photon circuit de comptage a été démontrée et montre une amélioration de l'efficacité de la photodétection, spécialement en ce qui concerne la sensibilité, la consommation d'énergie et le rapport signal sur bruit.----------ABSTRACT Optical brain imaging using functional near infra-red spectroscopy (fNIRS) offers a direct and noninvasive tool for monitoring of blood oxygenation. fNIRS is a noninvasive, safe, minimally intrusive, and high temporal-resolution technique for real-time and long-term brain imaging. It allows detecting both fast-neuronal and slow-hemodynamic signals. Besides the significant advantages of fNIRS systems, they still suffer from few drawbacks including low spatial- resolution, moderately high-level noise and high-sensitivity to movement. In order to overcome the limitations of currently available non-portable fNIRS systems, we have introduced a new low-power, miniaturized on-chip photodetector front-end intended for portable fNIRS systems. It includes silicon avalanche photodiode (SiAPD), Transimpedance amplifier (TIA), and Quench- Reset circuitry implemented using standard CMOS technologies to operate in both linear and Geiger modes. So it can be applied for both continuous-wave fNIRS (CW-fNIRS) and also single-photon counting applications. Several SiAPDs have been implemented in novel structures and shapes (Rectangular, Octagonal, Dual, Nested, Netted, Quadratic and Hexadecagonal) using different premature edge breakdown prevention techniques. The main characteristics of the SiAPDs are validated and the impact of each parameter and the device simulators (TCAD, COMSOL, etc.) have been studied based on the simulation and measurement results. Proposed techniques exhibit SiAPDs with high avalanche-gain (up to 119), low breakdown-voltage (around 12V) and high photon-detection efficiency (up to 72% in NIR region) in additional to a low dark- count rate (down to 30Hz at 1V excess bias voltage). Three new high gain-bandwidth product (GBW) and low-noise TIAs are introduced and implemented based on distributed-gain concept, logarithmic-amplification and automatic noise-rejection and have been applied in linear-mode of operation. The implemented TIAs offer a power-consumption around 0.4 mW, transimpedance gain of 169 dBΩ, and input-output current/voltage noises in fA/pV range accompanied with ability to tune the gain, bandwidth and power-consumption in a wide range. The implemented mixed quench-reset circuit (MQC) and controllable MQC (CMQC) front-ends offer a quenchtime of 10ns, a maximum power-consumption of 0.4 mW, with a controllable hold-off and resettimes. The on-chip integration of SiAPDs with TIA and photon-counting circuitries has been demonstrated showing improvement of the photodetection-efficiency, specially regarding to the sensitivity, power-consumption and signal-to-noise ratio (SNR) characteristics

NASA Tech Briefs, Winter 1977

Topics include: NASA TU Services: Technology Utilization services that can assist you in learning about and applying NASA technology; New Product Ideas: A summary of selected innovations of value to manufacturers for the development of new products; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Life Sciences; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences

The Journal of Microelectronic Research 2008

https://scholarworks.rit.edu/meec_archive/1016/thumbnail.jp