Thermodynamically Equivalent Silicon Models of Voltage-Dependent Ion Channels

We model ion channels in silicon by exploiting similarities between the thermodynamic principles that govern ion channels and those that govern transistors. Using just eight transistors, we replicate—for the first time in silicon—the sigmoidal voltage dependence of activation (or inactivation) and the bell-shaped voltage-dependence of its time constant. We derive equations describing the dynamics of our silicon analog and explore its flexibility by varying various parameters. In addition, we validate the design by implementing a channel with a single activation variable. The design’s compactness allows tens of thousands of copies to be built on a single chip, facilitating the study of biologically realistic models of neural computation at the network level in silicon

Neuronal Ion-Channel Dynamics in Silicon

We present a simple silicon circuit for modeling voltage-dependent ion channels found within neural cells, capturing both the gating particle\u27s sigmoidal activation (or inactivation) and the bell-shaped time constant. In its simplest form, our ion-channel analog consists of two MOS transistors and a unity-gain inverter. We present equations describing its nonlinear dynamics and measurements from a chip fabricated in a 0.25 /spl µ/m CMOS process. The channel analog\u27s simplicity allows tens of thousands to be built on a single chip, facilitating the implementation of biologically realistic models of neural computation

Neuromorphic silicon neuron circuits

23 páginas, 21 figuras, 2 tablas.-- et al.Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.This work was supported by the EU ERC grant 257219 (neuroP), the EU ICT FP7 grants 231467 (eMorph), 216777 (NABAB), 231168 (SCANDLE), 15879 (FACETS), by the Swiss National Science Foundation grant 119973 (SoundRec), by the UK EPSRC grant no. EP/C010841/1, by the Spanish grants (with support from the European Regional Development Fund) TEC2006-11730-C03-01 (SAMANTA2), TEC2009-10639-C04-01 (VULCANO) Andalusian grant num. P06TIC01417 (Brain System), and by the Australian Research Council grants num. DP0343654 and num. DP0881219.Peer Reviewe

Intrinsically biased electrocapacitive catalysis

We propose the application of the contact potential from metal-metal junctions or the built-in potential of semiconductor p-np-n junctions to induce or catalyze chemical reactions. Free of external sources, this intrinsic potential across microscale and nanoscale vacuum gaps establishes electric fields in excess of 10^7V/m. The electrostatic potential energy of these fields can be converted into useful chemical energy. As an example, we focus on the production of superthermal gas ions to drive reactions. Analysis indicates that this intrinsically biased electrocapacitive catalysis can achieve locally directed ion energies up to a few electron volts and local gas temperatureboosts in excess of 10^4K. Practical considerations for implementation and experimental tests are considered

Heteroepitaxy of semiconductor-insulator layers and their interface properties

The epitaxial growth of Ba₂SiO₄ thin films on Si(001) by co-deposition of Ba and Si in an oxygen background pressure is systematically investigated with a focus on the epitaxial interface. A structural investigation is performed by employing x-ray photoelectron spectroscopy (XPS), low energy electron diffraction (LEED) and aberration-corrected scanning transmission electron microscopy (STEM). In addition, an electrical characterization is done using MOS test capacitors. The stoichiometry at the interface turns out to be critically dependent on the oxygen background pressure during deposition. Films grown with an oxygen pressure just above the saturation point for a complete oxidation of the film still feature 1/4 ML of O atoms in Si-O-Si bonding states. In comparison, the Ba₂SiO₄ bulk structure has only O atoms in Si-O-Ba bonding states. STEM shows that these films form an atomically sharp interface to Si(001) and that the Ba₂SiO₄ bulk structure is maintained up to the penultimate layer at the interface. Only one silicate layer is changed to a (2x3) structure, which is also observed in LEED, to match the (2x1.5) bulk structure to Si(001), neglecting relaxations. An interface model is proposed for these films, which features a pseudo-(2x1) reconstruction of the Si surface and helps to understand the formation process of the epitaxial interface in greater detail. The growth in a high oxygen pressure leads to the formation of Si-rich silicate at the interface, which does not prevent the epitaxial growth but modifies the interface into a (2x6) structure. Moreover, a Ba surplus results in the formation of interfacial silicide, which is characterized by a (4x2) structure. A dielectric constant of k=22.5 ± 1.1 is found for Ba₂SiO₄, as well as band offsets to Si(001) larger than 1.8 eV for crystalline layers. Moreover, leakage current densities as low as 2 ⋅ 10⁻⁶ A/cm² at -1 V are measured for a 10 nm thick film. Interface trap densities at midgap of (1.14 ± 0.78) ⋅ 10¹² eV⁻¹cm⁻¹² are measured for crystalline films with an abrupt interface. Amorphous films show slightly higher interface trap densities of (2.72 ± 0.82) ⋅ 10¹² eV⁻¹cm⁻¹² at midgap. A further reduction of the interface trap density is possible by incorporating a Si-rich silicate layer at the interface, which results in interface trap densities of (3.32 ± 0.45) ⋅ 10¹¹ eV⁻¹cm⁻¹² at midgap for crystalline layers. However, even though no SiO₂ forms at the interface, the epitaxial interface still contributes an offset of (0.56 ± 0.08) nm to the overall CET, which greatly limits the achievable minimum CET of the gate stack