Thermo-Mechanical Effects Of Thermal Cycled Copper Through Silicon Vias

The semiconductor industry is currently facing transistor scaling issues due to fabrication thresholds and quantum effects. In this \u27More-Than-Moore\u27 era, the industry is developing new ways to increase device performance, such as stacking chips for three-dimensional integrated circuits (3D-IC). The 3D-IC\u27s superior performance over their 2D counterparts can be attributed to the use of vertical interconnects, or through silicon vias (TSV). These interconnects are much shorter, reducing signal delay. However TSVs are susceptible to various thermo-mechanical reliability concerns. Heating during fabrication and use, in conjunction with coefficient of thermal expansion mismatch between the copper TSVs and silicon substrate, create harmful stresses in the system. The purpose of this work is to evaluate the signal integrity of Cu-TSVs and determine the major contributing factors of the signal degradation upon in-use conditions. Two series of samples containing blind Cu-TSVs embedded in a Si substrate were studied, each having different types and amounts of voids from manufacturing. The samples were thermally cycled up to 2000 times using three maximum temperatures to simulate three unique in-use conditions. S11 parameter measurements were then conducted to determine the signal integrity of the TSVs. To investigate the internal response from cycling, a protocol was developed for cross-sectioning the copper TSVs. Voids were measured using scanning electron microscope and focused ion beam imaging of the cross-sections, while the microstructural evolution of the copper was monitored with electron backscattering diffraction. An increase in void area was found to occur after cycling. This is thought to be the major contributing factor in the signal degradation of the TSVs, since no microstructural changes were observed in the copper

JUNO Conceptual Design Report

The Jiangmen Underground Neutrino Observatory (JUNO) is proposed to determine the neutrino mass hierarchy using an underground liquid scintillator detector. It is located 53 km away from both Yangjiang and Taishan Nuclear Power Plants in Guangdong, China. The experimental hall, spanning more than 50 meters, is under a granite mountain of over 700 m overburden. Within six years of running, the detection of reactor antineutrinos can resolve the neutrino mass hierarchy at a confidence level of 3-4$\sigma$, and determine neutrino oscillation parameters $\sin^2\theta_{12}$, $\Delta m^2_{21}$, and $|\Delta m^2_{ee}|$ to an accuracy of better than 1%. The JUNO detector can be also used to study terrestrial and extra-terrestrial neutrinos and new physics beyond the Standard Model. The central detector contains 20,000 tons liquid scintillator with an acrylic sphere of 35 m in diameter. $\sim$17,000 508-mm diameter PMTs with high quantum efficiency provide $\sim$75% optical coverage. The current choice of the liquid scintillator is: linear alkyl benzene (LAB) as the solvent, plus PPO as the scintillation fluor and a wavelength-shifter (Bis-MSB). The number of detected photoelectrons per MeV is larger than 1,100 and the energy resolution is expected to be 3% at 1 MeV. The calibration system is designed to deploy multiple sources to cover the entire energy range of reactor antineutrinos, and to achieve a full-volume position coverage inside the detector. The veto system is used for muon detection, muon induced background study and reduction. It consists of a Water Cherenkov detector and a Top Tracker system. The readout system, the detector control system and the offline system insure efficient and stable data acquisition and processing.Comment: 328 pages, 211 figure

Investigation into yield and reliability enhancement of TSV-based three-dimensional integration circuits

Three dimensional integrated circuits (3D ICs) have been acknowledged as a promising technology to overcome the interconnect delay bottleneck brought by continuous CMOS scaling. Recent research shows that through-silicon-vias (TSVs), which act as vertical links between layers, pose yield and reliability challenges for 3D design. This thesis presents three original contributions.The first contribution presents a grouping-based technique to improve the yield of 3D ICs under manufacturing TSV defects, where regular and redundant TSVs are partitioned into groups. In each group, signals can select good TSVs using rerouting multiplexers avoiding defective TSVs. Grouping ratio (regular to redundant TSVs in one group) has an impact on yield and hardware overhead. Mathematical probabilistic models are presented for yield analysis under the influence of independent and clustering defect distributions. Simulation results using MATLAB show that for a given number of TSVs and TSV failure rate, careful selection of grouping ratio results in achieving 100% yield at minimal hardware cost (number of multiplexers and redundant TSVs) in comparison to a design that does not exploit TSV grouping ratios. The second contribution presents an efficient online fault tolerance technique based on redundant TSVs, to detect TSV manufacturing defects and address thermal-induced reliability issue. The proposed technique accounts for both fault detection and recovery in the presence of three TSV defects: voids, delamination between TSV and landing pad, and TSV short-to-substrate. Simulations using HSPICE and ModelSim are carried out to validate fault detection and recovery. Results show that regular and redundant TSVs can be divided into groups to minimise area overhead without affecting the fault tolerance capability of the technique. Synthesis results using 130-nm design library show that 100% repair capability can be achieved with low area overhead (4% for the best case). The last contribution proposes a technique with joint consideration of temperature mitigation and fault tolerance without introducing additional redundant TSVs. This is achieved by reusing spare TSVs that are frequently deployed for improving yield and reliability in 3D ICs. The proposed technique consists of two steps: TSV determination step, which is for achieving optimal partition between regular and spare TSVs into groups; The second step is TSV placement, where temperature mitigation is targeted while optimizing total wirelength and routing difference. Simulation results show that using the proposed technique, 100% repair capability is achieved across all (five) benchmarks with an average temperature reduction of 75.2? (34.1%) (best case is 99.8? (58.5%)), while increasing wirelength by a small amount

DART: Dependable VLSI Test Architecture and Its Implementation

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.2012 IEEE International Test Conference, 5-8 November 2012, Anaheim, CA, US

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Enhanced electrodeposition for the filling of micro-vias

This thesis investigated the introduction of megasound (MS) (1MHz) acoustic technology as an enhanced agitation method of an electrolyte solution for the electrochemical deposition of copper (Cu), used in electroplating processes. The thesis, carried out at Merlin Circuit Technology Ltd, studied the possibility of improving processing capabilities for use in Printed Circuit Board (PCB) industrial manufacture. Prior laboratory experiments demonstrated increased metallisation of vertical interconnect access (via) features in a Printed Circuit Board (PCB), which, if applied within manufacturing, would enable increased connectivity throughout a PCB and result in cost savings. PCB manufacturing quality after MS-assisted Cu electroplating was assessed by measurements of the topography of the electrodeposits, using scanning electron microscopy and white-light interferometry. Cu plating rate changes were also measured on the surface of the PCB and inside the vias. After plating Cu with MS-assistance, the macro and microscale surface composition was demonstrated to alter due to the direct influence of the acoustic waves. Systematic characteristic of the surface was conducted by varying the settings of the acoustic transducer device as well as the process parameters including electrical current distribution, bath additive chemistry and solution temperature. MS processing was shown to produce unique Cu artefacts. Their deleterious formation was demonstrated to be influenced by acoustic standing waves and microbubble formations at the electrolyte solution/PCB interface. Causes of these artefacts, microfluidic streaming and cavitation, were also observed and controlled to reduce the creation of these artefacts. MS plating Cu down through-hole via (THV) and blind-via (BV) interconnects was shown to produce measureable benefits. These include, for THVs, a 700 % increase of Cu plating deposit thickness within a 175 μm diameter, depth-to-width aspect ratio (ar) of 5.7:1, compared with processing under no-agitation conditions. For BVs, a 60 % average increase in Cu deposition in 150 μm and 200 μm, ar 1:1, was demonstrated against plating under standard manufacturing conditions - bubble agitation and panel movement.Engineering and Physical Research Council (EPSRC) grant number EP/G037523/

トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation.北九州市立大

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Cosmic Origins (COR) Program Technology Development 2018

No abstract availabl