Rupture testing for the quality control of electrodeposited copper interconnections in high-speed, high-density circuits

Printed Wiring Multilayer Board (PWMLB) structures for high speed, high density circuits are prone to failure due to the microcracking of electrolytic copper interconnections. The failure can occur in the foil that makes up the inner layer traces or in the plated through holes (PTH) deposit that forms the layer to layer interconnections. It is shown that there are some distinctive differences in the quality of Type E copper and that these differences can be detected before its use in a PWMLB. It is suggested that the strength of some Type E copper can be very low when the material is hot and that it is the use of this poor quality material in a PWMLB that results in PTH and inner layer microcracking. Since the PWMLB failure in question are induced by a thermal stress, and since the poorer grades of Type E materials used in these structures are susceptible to premature failure under thermal stress, the use of elevated temperature rupture and creep rupture testing is proposed as a means for screening copper foil, or its PTH equivalent, in order to eliminate the problem of Type E copper microcracking in advanced PWMLBs

Analysis of Printed Circuit Boards strains using finite element analysis and digital image correlation

This paper investigates the use of digital image correlation (DIC) and finite element analysis for strain measurement on Printed Board Circuits (PCBs). Circuit boards (PCBs) are designed to mechanically support and electrically connect an electronic component assembly. Due to screw assemblies, the surface level differences on which the PCB is placed, the process of assembling the electronic components induces a certain state of stress and deformation in the PCB. The main components affected are microprocessors due to the way they are glued to PCBs with BGA - Ball grid arrays (BGA). Digital Image Correlation (DIC) is a full-field contactless optical method for measuring displacements and strain in experimental testing, based on the correlation of images taken during test. The experimental setup is realized with Dantec Q-400 system used for image capture and Istra 4D software for image correlations and data analyses. The maximum level of the obtained strain is compared with the allowable limit. Finite element analysis (FEA) is a numerical method of analysis for stresses and strain in structures of any given geometry

Arc tracking control in insulation systems for aeronautic applications: challenges, opportunities, and research needs

Next generation aircrafts will use more electrical power to reduce weight, fuel consumption, system complexity and greenhouse gas emissions. However, new failure modes and challenges arise related to the required voltage increase and consequent rise of electrical stress on wiring insulation materials, thus increasing the risk of electrical arc appearance. This work performs a critical and comprehensive review concerning arc tracking effects in wiring insulation systems, underlying mechanisms, role of materials and possible mitigation strategies, with a special focus on aircraft applications. To this end an evaluation of the scientific and technological state of the art is carried out from the analysis of theses, research articles, technical reports, international standards and white papers. This review paper also reports the limitations of existing insulation materials, standard test methods and mitigation approaches, while identifying the research needs to comply with the future demands of the aircraft industryPeer ReviewedPostprint (published version

MODELING RATE DEPENDENT DURABILITY OF LOW-Ag SAC INTERCONNECTS FOR AREA ARRAY PACKAGES UNDER TORSION LOADS

The thesis discusses modeling rate-dependent durability of solder interconnects under mechanical torsion loading for surface mount area array components. The study discusses an approach to incorporate strain-rate dependency in durability estimation for solder interconnects. The components under study are two configurations of BGAs (ball grid array) assembled with select lead-free solders. A torsion test setup is used to apply displacement controlled loads on the test board. Accelerated test load profile is experimentally determined. Torsion test is carried out for all the components under investigation to failure. Strain-rate dependent (Johnson-Cook model) and strain-rate independent, elastic-plastic properties are used to model the solders in finite element simulation. Damage model from literature is used to estimate the durability for SAC305 solder to validate the approach. Test data is used to extract damage model constants for SAC105 solder and extract mechanical fatigue durability curve

HARMONIC VIBRATION TESTING OF ELECTRONIC COMPONENTS ATTACHED TO PRINTED WIRING BOARDS WITH SAC305 AND EUTECTIC SnPb SOLDER

Ball grid arrays attached to printed wiring boards with conventional tin-lead solder (63/37) and one of the leading lead-free tin-silver-copper solders (SAC305) were tested at high and low load levels of harmonic vibration. Leadless chip resistors attached to printed wiring boards with conventional tin-lead solder and lead-free solders (SAC105 and SAC305, and tin-nickel-copper, SN100C) were tested at low levels of harmonic vibration. The tests were conducted near the natural frequency of the assemblies to accelerate testing and to generate high cycle fatigue failures in a reasonable amount of time. The results showed that there are nearly negligible differences in the high cycle fatigue life between the SnPb and SAC305 solders. SN100C and SAC105 were less durable. A master durability plot was generated for SAC305 and SnPb to confirm the negligible-difference between the solders. A safe area was defined be used as a design goal for survivablity for circuit board design

Reliability Assessment of Voided Microvias in High Density Interconnect Printed Circuit Boards under Thermo-Mechanical Stresses

Microvias allow signal and power transmission between layers in high density interconnection printed circuit boards. Presence of voiding in filled microvias due to defective manufacturing process has raised concerns in industry. Voids can vary widely in shape and size and have been observed in both stacked and single-level microvias. IPC standards have addressed the presence of voids in microvias using void size as the acceptance criterion. The purpose of this study is to determine how voiding affects the degradation of microvias; if void size is the only parameter that needs to be taken into consideration or void shape is important as well. Voided as well as non-voided microvias were tested using liquid-to-liquid thermal shock to understand the difference between behavior of voided and non-voided microvias under thermo-mechanical stresses

MODELING THE PHYSICS OF FAILURE FOR ELECTRONIC PACKAGING COMPONENTS SUBJECTED TO THERMAL AND MECHANICAL LOADING

This dissertation presents three separate studies that examined electronic components using numerical modeling approaches. The use of modeling techniques provided a deeper understanding of the physical phenomena that contribute to the formation of cracks inside ceramic capacitors, damage inside plated through holes, and to dynamic fracture of MEMS structures. The modeling yielded numerical substantiations for previously proposed theoretical explanations. Multi-Layer Ceramic Capacitors (MLCCs) mounted with stiffer lead-free solder have shown greater tolerance than tin-lead solder for single cycle board bending loads with low strain rates. In contrast, flexible terminations have greater tolerance than stiffer standard terminations under the same conditions. It has been proposed that residual stresses in the capacitor account for this disparity. These stresses have been attributed to the higher solidification temperature of lead free solders coupled with the CTE mismatch between the board and the capacitor ceramic. This research indicated that the higher solidification temperatures affected the residual stresses. Inaccuracies in predicting barrel failures of plated through holes are suspected to arise from neglecting the effects of the reflow process on the copper material. This research used thermo mechanical analysis (TMA) results to model the damage in the copper above the glass transition temperature (Tg) during reflow. Damage estimates from the hysteresis plots were used to improve failure predictions. Modeling was performed to examine the theory that brittle fracture in MEMS structures is not affected by strain rates. Numerical modeling was conducted to predict the probability of dynamic failure caused by shock loads. The models used a quasi-static global gravitational load to predict the probability of brittle fracture. The research presented in this dissertation explored drivers for failure mechanisms in flex cracking of capacitors, barrel failures in plated through holes, and dynamic fracture of MEMS. The studies used numerical modeling to provide new insights into underlying physical phenomena. In each case, theoretical explanations were examined where difficult geometries and complex material properties made it difficult or impossible to obtain direct measurements