223 research outputs found

    High performance low cost interconnections for flip chip attachment with electrically conductive adhesive. Final report

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    High Temperature LTCC based SiC Double-sided Cooling Power Electronic Module

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    This objective of this dissertation research is to investigate a module packaging technology for high temperature double-sided cooling power electronic module application. A high-temperature wire-bondless low-temperature co-fired ceramic (LTCC) based double-sided cooling power electronic module was designed, simulated and fabricated. In this module, the conventional copper base plate is removed to reduce the thermal resistance between the device junctions to the heat sink and to improve the reliability of the module by eliminating the large area solder joint between the power substrate and the copper base plate. A low-temperature co-fired ceramic (LTCC) substrate with cavities and vias is used as the dielectric material between the top and bottom substrates and it also serves as the die frame. A nano silver attach material is used to enable the high-temperature operation. Thermal and thermo-mechanical simulations were performed to evaluate the advantages of the LTCC double-sided power module structure and compared to other reported module structures and its wire-bonded counterpart. The junction-to-case thermal resistance for the power module without a copper base plate is 0.029oC/W, which is smaller than that of the power module with a copper base plate. Thermo-mechanical simulation reveals that double-sided cooling power modules generate higher thermal stresses when compared to that of the single-sided cooling power modules which indicates the trade-off between the junction temperature and the thermo-mechanical stress. Electrical and thermal characterizations were performed to test the functionality of the fabricated module using a 1200V rated voltage blocking capability. The forward and reverse characteristics of the SiC power MOSFET and SiC diode module were tested to 200°C and they demonstrated the functionality of the power module. The junction-to-ambient thermal resistance of the proposed module is shown to reduce by 11% compared to the wire-bonded equivalent which shows an improvement of the thermal performance of the double-sided cooling structure. Finally, the reliability of the several power substrates was evaluated based on the thermal stress and fatigue life simulation of the bonding layer to determine the mechanical weakest spots of the power module. Thermal cycling experiments were also conducted to validate the simulation results

    Mechanical and electrical characterisation of anisotropic conductive adhesive particles

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    This thesis presents research into the mechanical and electrical characterisation of Anisotropic Conductive Adhesive (ACA) particles and their behaviour within typical joints. A new technique has been developed for study of individual ACA particle mechanical and electrical performance when undergoing deformation. A study of the effects of planarity variations on individual electrical joints in real ACA assemblies is presented firstly, followed by the research on the mechanical deformation and electrical tests of individual ACA particles undergoing deformation. In the co-planarity research, experiments introducing deliberate rotation between a chip and substrate were designed and carried out to simulate planarity variations in ACA assemblies. There are two outputs from this part of the research. One is the planarity variation effects on individual electrical joints in ACA assemblies, and the other is the effect of bond thickness on the resistance of a real joint. [Continues.

    Study and analysis of state-of-the-art FCS-MPC strategies for thermal regulation of power converters

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    La degradación en los convertidores de potencia basados en silicio, enmarcados en sistemas de tracción eléctrica y fuentes de energías renovables, es un tema de estudio de especial interés para aquellas aplicaciones donde los fallos amenazan la seguridad de personas o donde el mantenimiento es particularmente costoso. Motivado por la influencia de los fallos en IGBTs sobre los fallos habituales en los convertidores de potencia comunes, este trabajo utiliza la herramienta software PLECS como marco de trabajo para la simulación de algoritmos de control predictivo basado en modelo con conjunto finito de acciones de control (FCS-MPC) que pretenden -simultáneamente a conseguir el seguimiento eléctrico- extender directa o indirectamente la vida útil de los IGBTs. El trabajo se enfoca principalmente a la simulación en ordenador de los algoritmos controlando un inversor de dos niveles conectado a una carga RL. Además, pretende también introducir la implementación de éstos sobre un microcontrolador para su estudio controlando el inversor simulado en la plataforma PLECS RT Box 1, con el fin último de poder desarrollar validaciones de los controladores basadas en técnicas Hardware-In-the-Loop.Degradation of silicon-based power electronics converters in traction and renewable energy systems is a topic of interest particularly where module failure supposes a safety threat or where maintenance becomes especially expensive. Motivated by the influence of IGBT aging in usual power converters, this work uses the software tool PLECS as framework to simulate Finite Control Set Model Predictive Control (FCSMPC) algorithms that, simultaneously to achieving a certain current tracking, aim to directly or indirectly extend IGBTs’ lifetime. Whilst the work focuses on offline simulation of the algorithms on PLECS, it also targets to pave the way to implement algorithms in a micro-controller and to study how they control a two-level inverter connected to a RL load simulated on a PLECS RT Box 1 platform. The ultimate goal is to develop validations based on Hardware-In-the-Loop techniques of the control algorithms.Universidad de Sevilla. Máster Universitario en Ingeniería Electrónica, Robótica y Automátic

    High-frequency characterization of embedded components in printed circuit boards

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    The embedding of electronic components is a three-dimensional packaging technology, where chips are placed inside of the printed circuit board instead of on top. The advantage of this technology is the reduced electronic interconnection length between components. The shorter this connection, the faster the signal transmission can occur. Different high-frequency aspects of chip embedding are investigated within this dissertation: interconnections to the embedded chip, crosstalk between signals on the chip and on the board, and interconnections running on top of or underneath embedded components. The high-frequency behavior of tracks running near embedded components is described using a broadband model for multilayer microstrip transmission lines. The proposed model can be used to predict the characteristic impedance and the loss of the lines. The model is based on two similar approximations that reduce the multilayer substrate to an equivalent single-layer structure. The per-unit-length shunt impedance parameters are derived from the complex effective dielectric constant, which is obtained using a variational method. A complex image approach results in the calculation of a frequency-dependent effective height that can be used to determine the per-unit-length resistance and inductance. A deliberate choice was made for a simple but accurate model that could easily be implemented in current high-frequency circuit simulators. Next to quasi-static electromagnetic simulations, a dedicated test vehicle that allows for the direct extraction of the propagation constant of these multilayer microstrips is manufactured and used to verify the model. The verification of the model using simulation and measurements shows that the proposed model slightly overestimates the loss of the measured multilayer microstrips, but is more accurate than the simulations in predicting the characteristic impedance

    45-nm SOI CMOS Bluetooth Electrochemical Sensor for Continuous Glucose Monitoring

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    Due to increasing rates of diabetes, non-invasive glucose monitoring systems will become critical to improving health outcomes for an increasing patient population. Bluetooth integration for such a system has been previously unattainable due to the prohibitive energy consumption. However, enabling Bluetooth allows for widespread adoption due to the ubiquity of Bluetooth-enabled mobile devices. The objective of this thesis is to demonstrate the feasibility of a Bluetooth-based energy-harvesting glucose sensor for contact-lens integration using 45~nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The proposed glucose monitoring system includes a Bluetooth transmitter implemented as a two-point closed loop PLL modulator, a sensor potentiostat, and a 1st-order incremental delta-sigma analog-to-digital converter (IADC). This work details the complete system design including derivation of top-level specifications such as glucose sensing range, Bluetooth protocol timing, energy consumption, and circuit specifications such as carrier frequency range, output power, phase-noise performance, stability, resolution, signal-to-noise ratio, and power consumption. Three test chips were designed to prototype the system, and two of these were experimentally verified. Chip 1 includes a partial implementation of a phase-locked-loop (PLL) which includes a voltage-controlled-oscillator (VCO), frequency divider, and phase-frequency detector (PFD). Chip 2 includes the design of the sensor potentiostat and IADC. Finally, Chip 3 combines the circuitry of Chip 1 and Chip 2, along with a charge-pump, loop-filter and power amplifier to complete the system. Chip 1 DC power consumption was measured to be 204.8~μ\muW, while oscillating at 2.441 GHz with an output power PoutP_{out} of -35.8 dBm, phase noise at 1 MHz offset L(1 MHz)L(1\text{ MHz}) of -108.5 dBc/Hz, and an oscillator figure of merit (FOM) of 183.44dB. Chip 2 achieves a total DC power consumption of 5.75~μ\muW. The system has a dynamic range of 0.15~nA -- 100~nA at 10-bit resolution. The integral non-linearity (INL) and differential non-linearity (DNL) of the IADC were measured to be -6~LSB/±\pm0.3~LSB respectively with a conversion time of 65.56~ms. This work achieves the best duty-cycled DC power consumption compared to similar glucose monitoring systems, while providing sufficient performance and range using Bluetooth

    Mechanical behaviour and reliability of Sn3.8AgO.7Cu solder for a surface mount assembly

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    The demands for compact, light weight and Iow cost electronic products have resulted in the miniaturisation of solder interconnects to a sub-millimetre scale. With such a reduction in size, the solder joints cannot be assumed to behave in the same way as bulk solder in terms of reliability due to the fact that their material behaviours are influenced by the joint size and microstructure. The complexity of their reliability assessment is furthermore compounded by the demand for the replacement of traditional SnPb solder alloys with lead-free alloys, due to the presence of the toxic and health hazardous element (Pb) in the former alloy. However, these new lead-free alloys have much less history of industrial applications, and their material and reliability data is not as well developed as traditional lead-based alloys. In addition, most previous reliability assessments using finite element analysis have assumed a uniform distribution of temperature within the electronic assembly, which conflicts the actual temperature conditions during circuit operation. Therefore, this research was undertaken to analyse the effect of solder joint size on solder material properties from which material models were developed, and to determine the effect of an actual (nonuniform) temperature distribution in an electronic assembly on the reliability of its solder joints. Following a review of lead-free solders and potential lead-free alloys, lead-free solder microstructures, and the reliability issues and factors affecting the reliability of solder joints, the practical aspects of this research were carried out in two main parts. The first part consisted of substantial work on the experimental determination of the temperature distribution in a typical surface mount chip resistor assembly for power cycling conditions, and the stress-strain and creep behaviour for both Sn3.8AgO.7Cu solder joints and reflowed bulk solder. This also included building material models based on the experimental data for the solder joints tested and comparison with that for bulk solder. Based on the comparison of the material properties, two extreme material models were selected for the reliability study. Size and microstructure effects on the solder material properties were also discussed in this part. The second part comprised of extensive finite element analysis of a surface mount chip resistor assembly and reliability assessment of its solder joints. The simulation began with elasto-plastic analysis for 2D and 3D chip resistor assemblies to decide upon the kind of formulation to be used when the full complexity of both plasticity and creep is considered. The simulation was carried out considering the determined non-uniform temperature distribution and idealized or traditional uniform temperature condition. The solder joint's material properties were modelled using the two material models determined from the experimental results. The effect of temperature distribution during thermal cycling and of the selected material models on the solder joint reliability was demonstrated using finite element analysis and subsequent fatigue life estimation. In summary, this research has concluded that the material behaviour of the solder joint is different from that of bulk solder due to the effect of its size and microstructure. The anisotropic behaviour of the solder joint cannot be ignored in reliability studies, since it has a significant effect on the solder joint's fatigue life. The research also showed the significant effect of an actual (non-uniform) temperature distribution in the electronic assembly on the solder joint fatigue life

    Digital neural circuits : from ions to networks

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    PhD ThesisThe biological neural computational mechanism is always fascinating to human beings since it shows several state-of-the-art characteristics: strong fault tolerance, high power efficiency and self-learning capability. These behaviours lead the developing trend of designing the next-generation digital computation platform. Thus investigating and understanding how the neurons talk with each other is the key to replicating these calculation features. In this work I emphasize using tailor-designed digital circuits for exactly implementing bio-realistic neural network behaviours, which can be considered a novel approach to cognitive neural computation. The first advance is that biological real-time computing performances allow the presented circuits to be readily adapted for real-time closed-loop in vitro or in vivo experiments, and the second one is a transistor-based circuit that can be directly translated into an impalpable chip for high-level neurologic disorder rehabilitations. In terms of the methodology, first I focus on designing a heterogeneous or multiple-layer-based architecture for reproducing the finest neuron activities both in voltage-and calcium-dependent ion channels. In particular, a digital optoelectronic neuron is developed as a case study. Second, I focus on designing a network-on-chip architecture for implementing a very large-scale neural network (e.g. more than 100,000) with human cognitive functions (e.g. timing control mechanism). Finally, I present a reliable hybrid bio-silicon closed-loop system for central pattern generator prosthetics, which can be considered as a framework for digital neural circuit-based neuro-prosthesis implications. At the end, I present the general digital neural circuit design principles and the long-term social impacts of the presented work
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