Research Activities of JWRI

Abstracts of the Article

State detection of bond wires in IGBT modules using eddy current pulsed thermography

Insulated gate bipolar transistor (IGBT) modules are important safety critical components in electrical power systems. Bond wire lift-off, a plastic deformation between wire bond and adjacent layers of a device caused by repeated power/thermal cycles, is the most common failure mechanism in IGBT modules. For the early detection and characterization of such failures, it is important to constantly detect or monitor the health state of IGBT modules, and the state of bond wires in particular. This paper introduces eddy current pulsed thermography (ECPT), a nondestructive evaluation technique, for the state detection and characterization of bond wire lift-off in IGBT modules. After the introduction of the experimental ECPT system, numerical simulation work is reported. The presented simulations are based on the 3-D electromagnetic-thermal coupling finite-element method and analyze transient temperature distribution within the bond wires. This paper illustrates the thermal patterns of bond wires using inductive heating with different wire statuses (lifted-off or well bonded) under two excitation conditions: nonuniform and uniform magnetic field excitations. Experimental results show that uniform excitation of healthy bonding wires, using a Helmholtz coil, provides the same eddy currents on each, while different eddy currents are seen on faulty wires. Both experimental and numerical results show that ECPT can be used for the detection and characterization of bond wires in power semiconductors through the analysis of the transient heating patterns of the wires. The main impact of this paper is that it is the first time electromagnetic induction thermography, so-called ECPT, has been employed on power/electronic devices. Because of its capability of contactless inspection of multiple wires in a single pass, and as such it opens a wide field of investigation in power/electronic devices for failure detection, performance characterization, and health monitoring

Transistor step stress testing program for JANTX2N2905A

The effect of power/temperature step stress when applied to the transistor JANTX2N2905A manufactured by Texas Instruments and Motorola is reported. A total of 48 samples from each manufacturer was submitted to the process outlined. In addition, two control sample units were maintained for verification of the electrical parametric testing. All test samples were subjected to the electrical tests outlined in Table 2 after completing the prior power/temperature step stress point

Assessment of partial discharge activity and conductivity in IGBT modules as a reliability index

Al giorno d’oggi l’elettronica di potenza deve essere in grado di operare in ambienti ostili e in condizioni di lavoro difficili. Il tema dell’affidabilità è diventato fondamentale quanto quello dell’efficienza. Questa tesi si focalizza sull’IGBT, in particolare sul suo sistema d’isolamento. Il primo passo è stato studiare in dettaglio i meccanismi di guasto possibili e più frequenti. Dal momento che le scariche parziali risultano essere un problema per l’affidabilità dei dielettrici solidi, in questo studio si esamina l’attività di PD su moduli IGBT nuovi ed invecchiati, in diverse configurazioni, con forme d’onda di tensione e temperature differenti. Si sono effettuate anche misure di corrente di dispersione su moduli nuovi ed invecchiati alla temperatura di lavoro. I risultati sono stati post-processati statisticamente tentando di ottenere indici di affidabilità per quei moduli. Quasi tutti i moduli invecchiati sono interessati da PD e i risultati mostrano che il PDIV, assieme ad altri fattori, è sicuramente influenzato dall’ageing. I risultati del monitoraggio della corrente di dispersione mostrano una tendenza all'aumento con l'invecchiamento. Si sono svolte anche simulazioni con software agli elementi finiti e rilevazioni ottiche di PD ed entrambe supportano i risultati ottenuti. È necessario effettuare ulteriori indagini su un data set più ampio al fine di migliorare un algoritmo di diagnostica predittiva basato sui valori di PDIV e conducibilità

Experimental Characterization Of Cu Free-Air Ball And Simulations Of Dielectric Fracture During Wire Bonding

Wire bonding is the process of forming electrical connection between the integrated circuit (IC) and its structural package. ICs made of material with low dielectric constant (low-k) and ultra low-k are porous in nature, and are prone to fracture induced failure during packaging process. In recent years, there is increasing interest in copper wire bond technology as an alternative to gold wire bond in microelectronic devices due to its superior electrical performance and low cost. Copper wires are also approximately 25% more conductive than Au wires aiding in better heat dissipation. At present, validated constitutive models for the strain rate and temperature dependent behavior of Cu free-air ball (FAB) appear to be largely missing in the literature. The lack of reliable constitutive models for the Cu FAB has hampered the modeling of the wire bonding process and the ability to assess risk of fracture in ultra low-k dielectric stacks. The challenge to FAB characterization is primarily due to the difficulty in performing mechanical tests on spherical FAB of micrometers in size. To address this challenge, compression tests are performed on FAB using custom-built microscale tester in the current study. Specifically, the tester has three closed-loop controlled linear stages with submicron resolution, a manual tilt stage, a six-axis load cell with sub-Newton load resolution for eliminating misalignment, a milliNewton resolution load cell for compression load measurement, a capacitance sensor to estimate sample deformation and to control the vertical stage in closed loop, a high working depth camera for viewing the sample deformation, and controllers for the stages implemented in the LabVIEW environment. FAB is compressed between tungsten carbide punches and a constitutive model is developed for Cu FAB through an inverse modeling procedure. In the inverse procedure, appropriate constitutive model parameter values are iterated through an automated optimization workflow, until the load-displacement response matches the experimentally observed response. Using the material properties obtained from the experiment, a macroscale finite element model for the impact and ulatrasonic vibration stages of wire bonding process is constructed to simulate (a) Plastic deformation of the Cu FAB at different time steps (b) Evolution of contact pressure (c) Phenomenon such as pad splash and lift-off. The deformations from the macroscale model are provided as input to a microscale model of the dielectric with copper vias as well as line-type heterogeneities. The microscale model is used to identify potential crack nucleation sites as well as the crack path within the ILD stack during wire bonding. The modeling provides insight into the relative amounts of damage accumulated during the impact and the ultrasonic excitation stages. In general, Bonding over Active Circuit (BOAC) has made wire bonding a considerable challenge due to the brittleness of the dielectric. Identifying and locating microscale fractures beneath the bond pads during wire bonding require extensive sample preparation and investigation for microscopic characterization. While simulations of fracture are an attractive alternative to trial and error microscopic characterization, the length scale of components involved in wire bonding varies from millimeters to nanometers. Therefore, constructing a finite element mesh across the model is computationally costly. Also, a multi-scale simulation framework is necessary. Such a modeling framework is also developed in this work to predict crack nucleation and propagation in wire bond induced failure

Converter- and Module-level Packaging for High Power Density and High Efficiency Power Conversion

Advancements in the converter- and module-level packaging will be the key for the development of the emerging high-power, high power-density, high-eciency power conversion applications, such as traction, shipboards, more-electric-aircraft, and locomotive. Wide bandgap (WBG) devices such as silicon carbide (SiC) MOSFET attract much attention in these applications for their fast switching speeds, resulting in low loss and a consequent possibility for high switching frequency to increase the power density. However, for high-current, high power implementations, WBG devices are still available in small die sizes. Multiple SiC devices need to be connected in parallel to replace a large IGBT die. It is challenging to realize high-switching-frequency and low loss with a lot of parallel devices due to the inherent parameter dierences, which lead to unbalanced dynamic current sharing resulting in unequal temperature distribution and overstress. Apart from the technical challenges, the price of SiC modules is another roadblock for its widespread application. The paralleling of a large number of SiC chips in the module to handle high current increases the module cost. Hence, this work proposes a Si-IGBT and SiC-MOSFET-based hybrid switch solution. For a converter-level packaging, the device technology, available device package, and orientation of the pins are the essential governing factors. This work addresses the converter-level packaging, which is referred to as a power electronics building block, of the proposed hybrid switch, combining discrete packages and frame-based modules for the devices and a singlephase three-level T-type topology. The primary optimization objective for converter-level packaging includes low inductance busbar design, high eciency, and high specic and volumetric power density. Overall implementation is not trivial; however, this work achieves an optimum design compared to the state-of-the-art. The module-level packaging challenges are dependent on the type of device technology and topology. Reducing the parasitic inductances, capacitances, and the junction to case thermal resistance are the optimization objectives in module packaging. Given the intended application of the module, achieving a high-reliability module is also essential. This work includes a hybrid switch-based power module addressing the challenges of WBG module-level packaging and challenges specic to the hybrid switch. The availability of engineering samples of SiC MOSFETs with voltage ratings above 10 kV and commercialization in the future drive the module-level packaging of high voltage devices. High voltage power modules will support the development of future solid-state circuit breakers, transformers, and power conversion applications in shipboards and rolling stocks. The availability of these modules can eliminate the necessity of multilevel topologies. This work investigates and demonstrates the module-level packaging of HV (10-15 kV) SiC MOSFETs

Apollo experience report guidance and control systems: Primary guidance, navigation, and control system development

The primary guidance, navigation, and control systems for both the lunar module and the command module are described. Development of the Apollo primary guidance systems is traced from adaptation of the Polaris Mark II system through evolution from Block I to Block II configurations; the discussion includes design concepts used, test and qualification programs performed, and major problems encountered. The major subsystems (inertial, computer, and optical) are covered. Separate sections on the inertial components (gyroscopes and accelerometers) are presented because these components represent a major contribution to the success of the primary guidance, navigation, and control system

How to protect a wind turbine from lightning

Techniques for reducing the chances of lightning damage to wind turbines are discussed. The methods of providing a ground for a lightning strike are discussed. Then details are given on ways to protect electronic systems, generating and power equipment, blades, and mechanical components from direct and nearby lightning strikes