Stress-Induced Delamination Of Through Silicon Via Structures

Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effect of thermal stresses on interfacial reliability of TSV structures. First, the three-dimensional distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semi-analytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results obtained by finite element analysis (FEA). Results from the stress analysis suggest interfacial delamination as a potential failure mechanism for the TSV structure. Analytical solutions for various TSV designs are then obtained for the steady-state energy release rate as an upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. Based on these results, the effects of TSV designs and via material properties on the interfacial reliability are elucidated. Finally, potential failure mechanisms for TSV pop-up due to interfacial fracture are discussed.Aerospace Engineerin

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Development and Packaging of Microsystems Using Foundry Services

Micro-electro-mechanical systems (MEMS) are a new and rapidly growing field of research. Several advances to the MEMS state of the art were achieved through design and characterization of novel devices. Empirical and theoretical model of polysilicon thermal actuators were developed to understand their behavior. The most extensive investigation of the Multi-User MEMS Processes (MUMPs) polysilicon resistivity was also performed. The first published value for the thermal coefficient of resistivity (TCR) of the MUMPs Poly 1 layer was determined as 1.25 x 10(exp -3)/K. The sheet resistance of the MUMPs polysilicon layers was found to be dependent on linewidth due to presence or absence of lateral phosphorus diffusion. The functional integration of MEMS with CMOS was demonstrated through the design of automated positioning and assembly systems, and a new power averaging scheme was devised. Packaging of MEMS using foundry multichip modules (MCMs) was shown to be a feasible approach to physical integration of MEMS with microelectronics. MEMS test die were packaged using Micro Module Systems MCM-D and General Electric High Density Intercounect and Chip-on-Flex MCM foundries. Xenon difluoride (XeF2) was found to be an excellent post-packaging etchant for bulk micromachined MEMS. For surface micromachining, hydrofluoric acid (HF) can be used

Numerical Modeling Analysis of Wafer Warpage and Carrier Mobility Change due to Tapered Through-Silicon-Via Geometry

Three-dimensional integration is a solution that vertically stacks multiple layers of silicon chips by Through-Silicon-Vias (TSVs) to enhance the performance of microelectronic devices. The tapered TSV profile can help to overcome the technical difficulties. However, an easily overlooked issue is that tapered TSV can cause wafer warpage during the fabrication processes. Wafer warpage can cause chip misalignment and impose additional deformation. In an effort to investigate the TSV geometric effect, a large number of finite element analysis (FEA) simulations were performed to quantify the thermal stress distribution and the thermally induced curvature. It was found that the tapered geometry alone can induce significant wafer bending, which has not been reported by other researchers. The effect of taper angle, TSV radius, TSV pitch, and wafer thickness were quantitatively studied. In addition, the incorporations of anisotropic silicon property and intermediate layers between the copper TSV and silicon into the numerical models were assessed. Thermally induced stress concentration around copper TSV near the wafer surface can lead to degradation of the device performance by affecting the carrier mobility in transistors. This piezoresistivity effect can cause serious reliability concerns. The size of keep-out zone (KOZ), which is identified as a threshold of 5% carrier mobility change, was also quantified for various transistor types in different channel directions

Using confocal microscopy and digital image correlation to measure local strains around a chip corner and a crack front

Abstract: In a flip chip package, the chip corner areas which are embedded in the underfill material are often critical to the damage initiation, since a stress concentration usually exists at these locations. A high level of stress concentration often promotes crack initiation from the chip corner. In order to better understand the local deformation around chip corners and crack tips, a method based on laser scanning confocal microscopy combined with the digital image correlation (confocal-DIC) was developed to measure local strain directly in deformed, transparent objects. A transparent epoxy resin with alumina particle fillers was used in four different types of samples, which were fabricated for the purpose of validation. A non-constrained sample and a thin-layer sample were used to verify the isotropic thermal expansion and the strain gradients with respect to the depth, respectively. Results from both samples were in good agreements with the calculation from the coefficient of thermal expansion (CTE) and FEM simulations. Furthermore, the confocal-DIC technique was applied to measure the strain distribution near the chip corner area of a third sample replicating the geometry of a flip chip package. The measured maximum first principal strain was located at the chip corner, reaching 0.9 % at 60 °C, in a good agreement with the simulation results. The strain in front of the crack tip was also evaluated by a three-point bending test in a fourth test sample. The measured maximum strain was 5.8±0.7 %, corresponding to a relative error of only about 5 % compared to simulations for a round crack tip configuration. The averaging used in DIC lowers its spatial resolution and makes it difficult to capture higher strain gradients in small regions. However, the confocal-DIC approach appears to be able to provide reasonable results for evaluating the maximum strain and the full field strain distribution in tri-dimensional volumes with geometries, materials and dimensions which are very similar to those of actual flip chip microelectronic packages

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs

Beam lead technology

Beam lead technology for microcircuit interconnections with applications to metallization, passivation, and bondin

Study and characetrization of plastic encapsulated packages for MEMS

Technological advancement has thrust MEMS design and fabrication into the forefront of modern technologies. It has become sufficiently self-sustained to allow mass production. The limiting factor which is stalling commercialization of MEMS is the packaging and device reliability. The challenging issues with MEMS packaging are application specific. The function of the package is to give the MEMS device mechanical support, protection from the environment, and electrical connection to other devices in the system. The current state of the art in MEMS packaging transcends the various packaging techniques available in the integrated circuit (IC) industry. At present the packaging of MEMS includes hermetic ceramic packaging and metal packaging with hermetic seals. For example the ADXL202 accelerometer from the Analog Devices. Study of the packaging methods and costs show that both of these methods of packaging are expensive and not needed for majority of MEMS applications. Due to this the cost of current MEMS packaging is relatively high, as much as 90% of the finished product. Reducing the cost is therefore of the prime concern. This Thesis explores the possibility of an inexpensive plastic package for MEMS sensors like accelerometers, optical MEMS, blood pressure sensors etc. Due to their cost effective techniques, plastic packaging already dominates the IC industry. They cost less, weigh less, and their size is small. However, porous nature of molding materials allows penetration of moisture into the package. The Thesis includes an extensive study of the plastic packaging and characterization of three different plastic package samples. Polymeric materials warp upon absorbing moisture, generating hygroscopic stresses. Hygroscopic stresses in the package add to the thermal stress due to high reflow temperature. Despite this, hygroscopic characteristics of the plastic package have been largely ignored. To facilitate understanding of the moisture absorption, an analytical model is presented in this Thesis. Also, an empirical model presents, in this Thesis, the parameters affecting moisture ingress. This information is important to determine the moisture content at a specific time, which would help in assessing reliability of the package. Moisture absorption is modeled using the single phase absorption theory, which assumes that moisture diffusion occurs freely without any bonding with the resin. This theory is based on the Fick\u27s Law of diffusion, which considers that the driving force of diffusion is the water concentration gradient. A finite difference simulation of one-dimensional moisture diffusion using the Crank-Nicolson implicit formula is presented. Moisture retention causes swelling of compounds which, in turn, leads to warpage. The warpage induces hygroscopic stresses. These stresses can further limit the performance of the MEMS sensors. This Thesis also presents a non invasive methodology to characterize a plastic package. The warpage deformations of the package are measured using Optoelectronic holography (OEH) methodology. The OEH methodology is noninvasive, remote, and provides results in full-field-of-view. Using the quantitative results of OEH measurements of deformations of a plastic package, pressure build up can be calculated and employed to assess the reliability of the package

Tunable Copper Microstructures in Blanket Films and Trenches Using Pulsed Electrodeposition

Copper interconnects in microelectronics have long been plagued with thermo-mechanical reliability issues. Control over the copper deposition process and resulting microstructure can dictate its material properties and reduce stresses as well as defects that form in the copper. In this thesis, pulse electrodeposition processing parameters were evaluated for their impact on the copper microstructure (grain size, texture, and twin density and stress state) through electron backscattering diffraction and wafer curvature measurements. Varying levels of constraint were also investigated for their effect on the copper microstructure to better understand the microstructures of more complex three-dimensional interconnects. Highly texture blanket copper films were deposited with various pulse frequencies and duty cycle, which was found to control grain size, orientation, and twin density. Higher twin densities were also observed in the films with lower residual stress. The findings from blanket film studies were carried over to trench deposited samples, where the influence of organic additives, typically used in the electrolytic bath to produce defect-free filling of advanced geometries, on the copper microstructure was studied. With the addition of organic additives, depositions produced finer grained structures with an increased contribution from the microstructure of the trench sidewall seed layer, especially with increasing trench aspect ratio. In addition, the increased constraint of the copper, resulted in larger stresses within the features and higher twin densities. The core of this dissertation demonstrated the ability to alter the resulting Cu microstructure through variations in pulse electrodeposition parameters