Theoretical Design and FPGA-Based Implementation of Higher-Dimensional Digital Chaotic Systems

Traditionally, chaotic systems are built on the domain of infinite precision in mathematics. However, the quantization is inevitable for any digital devices, which causes dynamical degradation. To cope with this problem, many methods were proposed, such as perturbing chaotic states and cascading multiple chaotic systems. This paper aims at developing a novel methodology to design the higher-dimensional digital chaotic systems (HDDCS) in the domain of finite precision. The proposed system is based on the chaos generation strategy controlled by random sequences. It is proven to satisfy the Devaney's definition of chaos. Also, we calculate the Lyapunov exponents for HDDCS. The application of HDDCS in image encryption is demonstrated via FPGA platform. As each operation of HDDCS is executed in the same fixed precision, no quantization loss occurs. Therefore, it provides a perfect solution to the dynamical degradation of digital chaos.Comment: 12 page

Bifurcations and synchronization using an integrated programmable chaotic circuit

This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic behaviors by changing a few external bias currents. In particular, by changing one of these bias currents, the chip provides different examples of a period-doubling route to chaos. We present experimental orbits and attractors, time waveforms and power spectra measured from the chip. By using two chip units, experiments on synchronization can be carried out as well in real-time. Measurements are presented for the following synchronization schemes: linear coupling, drive-response and inverse system. Experimental statistical characterizations associated to these schemes are also presented. We also outline the possible use of the chip for chaotic encryption of audio signals. Finally, for completeness, the paper includes also a brief description of the chip design procedure and its internal circuitry

Analysis and implementation of fractional-order chaotic system with standard components

This paper is devoted to the problem of uncertainty in fractional-order Chaotic systems implemented by means of standard electronic components. The fractional order element (FOE) is typically substituted by one complex impedance network containing a huge number of discrete resistors and capacitors. In order to balance the complexity and accuracy of the circuit, a sparse optimization based parameter selection method is proposed. The random error and the uncertainty of system implementation are analyzed through numerical simulations. The effectiveness of the method is verified by numerical and circuit simulations, tested experimentally with electronic circuit implementations. The simulations and experiments show that the proposed method reduces the order of circuit systems and finds a minimum number for the combination of commercially available standard components.This work was supported in part by the National Natural Science Foundation of China under Grant 61501385, in part by the National Nuclear Energy Development Project of State Administration for Science, Technology and Industry for National Defense, PRC under Grant 18zg6103, and in part by Sichuan Science and Technology Program under Grant 2018JY0522. We would like to thank Xinghua Feng for meaningful discussion.info:eu-repo/semantics/publishedVersio

Effective synchronization of a class of Chua's chaotic systems using an exponential feedback coupling

In this work a robust exponential function based controller is designed to synchronize effectively a given class of Chua's chaotic systems. The stability of the drive-response systems framework is proved through the Lyapunov stability theory. Computer simulations are given to illustrate and verify the method.Comment: 12 pages, 18 figure

Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.Comisión Interministerial de Ciencia y Tecnología TIC 96-1392-CO2-

Analysis and implementation of fractional-order chaotic system with standard components

This paper is devoted to the problem of uncertainty in fractional-order Chaotic systems implemented by means of standard electronic components. The fractional order element (FOE) is typically substituted by one complex impedance network containing a huge number of discrete resistors and capacitors. In order to balance the complexity and accuracy of the circuit, a sparse optimization based parameter selection method is proposed. The random error and the uncertainty of system implementation are analyzed through numerical simulations. The effectiveness of the method is verified by numerical and circuit simulations, tested experimentally with electronic circuit implementations. The simulations and experiments show that the proposed method reduces the order of circuit systems and finds a minimum number for the combination of commercially available standard components.This work was supported in part by the National Natural Science Foundation of China under Grant 61501385, in part by the National Nuclear Energy Development Project of State Administration for Science, Technology and Industry for National Defense, PRC under Grant 18zg6103, and in part by Sichuan Science and Technology Program under Grant 2018JY0522. We would like to thank Xinghua Feng for meaningful discussion.info:eu-repo/semantics/publishedVersio