Sputter deposition of thin-film capacitors onto low temperature co-fired ceramic substrates

Single layer thin film capacitor structures were fabricated on the surface of low temperature co-fired ceramic (LTCC) substrates using sputter deposition. The capacitor structures had areas between ~10⁴ µm² to ~10⁶ µm² and featured ~200 nm Al or Pt electrodes with 150-1500 nm Al₂O₃ dielectric layers. Impedance analysis and current-voltage testing were carried out to determine the effect of electrode material and dielectric thickness upon capacitor performance. Capacitance values for devices with Al electrodes ranged from ~10 to ~700 pF, depending on capacitor area and dielectric thickness, and the fit to expected values was better than devices with Pt or mixed (one Al, one Pt) electrodes. Dielectric loss increased with increasing Al₂O₃ thickness, most likely due to cracking in thick (\u3e1 µm) sputtered films. All measured loss values for the sputter deposited Al₂O₃ (tan[lambda]~0.02) were greater than bulk Al₂O₃ (tan[lambda] ~0.001). Transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) were utilized to examine selected capacitor structures. Electron beam induced crystallization of amorphous Al₂O₃ was observed during the selected area diffraction (SAD) patterns. TEM examination and impedance analysis both confirm that functional capacitors with Al electrodes and 300 - 000 nm thick Al₂O₃ dielectric layers can be fabricated on LTCC substrates using sputter deposition --Abstract, page iv

Ultrathin CaTiO3 Capacitors: Physics and Application

Scaling of electronic circuits from micro- to nanometer size determined the incredible development in computer technology in the last decades. In charge storage capacitors that are the largest components in dynamic random access memories (DRAM), dielectrics with higher permittivity (high-k) were needed to replace SiO2. Therefore ZrO2 has been introduced in the capacitor stack to allow sufficient capacitance in decreasing structure sizes. To improve the capacitance density per cell area, approaches with three dimensional structures were developed in device fabrication. To further enable scaling for future generations, significant efforts to replace ZrO2 as high-k dielectric have been undertaken since the 1990s. In calculations, CaTiO3 has been identified as a potential replacement to allow a significant capacitance improvement. This material exhibits a significantly higher permittivity and a sufficient band gap. The scope of this thesis is therefore the preparation and detailed physical and electrical characterization of ultrathin CaTiO3 layers. The complete capacitor stacks including CaTiO3 have been prepared under ultrahigh vacuum to minimize the influence of adsorbents or contaminants at the interfaces. Various electrodes are evaluated regarding temperature stability and chemical reactance to achieve crystalline CaTiO3. An optimal electrode was found to be a stack consisting of Pt on TiN. Physical experiments confirm the excellent band gap of 4.0-4.2 eV for ultrathin CaTiO3 layers. Growth studies to achieve crystalline CaTiO3 indicate a reduction of crystallization temperature from 640°C on SiO2 to 550°C on Pt. This reduction has been investigated in detail in transmission electron microscopy measurements, revealing a local and partial epitaxial growth of (111) CaTiO3 on top of (111) Pt surfaces. This preferential growth is beneficial to the electrical performance with an increased relative permittivity of 55 with the advantage of a low leakage current comparable to that in amorphous CaTiO3 layers. A detailed electrical analysis of capacitors with amorphous and crystalline CaTiO3 reveals a relative permittivity of 30 for amorphous and an excellent value of 105 for fully crystalline CaTiO3. The permittivity exhibits a quadratic dependence with applied electric field. Crystalline CaTiO3 shows a 1-3% drop in capacitance density and permittivity at a bias voltage of 1V, which is significantly lower compared to all results for SrTiO3 capacitors measured elsewhere. A capacitance equivalent thickness (CET) below 1.0 nm with current densities 1×10−8 A/cm2 have been achieved on carbon electrodes. Finally, CETs of about 0.5 nm with leakage currents of 1 × 10−7 A/cm2 on top of Pt/TiN fulfill the 2016 DRAM requirements following the ITRS road map of 2012.Die Verkleinerung von elektronischen Bauelementen hin zu nanometerkleinen Strukturen beschreibt die unglaubliche Entwicklung der Computertechnologie in den letzten Jahrzehnten. In Ladungsspeicherkondensatoren, den größten Komponenten in Arbeitsspeichern, wurden dafür Dielektrika benötigt, die eine deutlich höhere Permittivität als SiO2 besitzen. ZrO2 wurde als geeignetes Dielektrikum eingeführt, um eine ausreichende Kapazität bei kleiner werdenen Strukturen sicherzustellen. Zur weiteren Verbesserung der Kapazitätsdichte pro Zellfläche konnten 3D Strukturen in die Chipherstellung integriert werden. Seit den 1990ern wurden parallel bedeutende Anstrengungen unternommen, um ZrO2 als Dielektrikum durch Materialien mit noch höherer Permittivität zu ersetzen. Nach Berechnungen stellt nun CaTiO3 eine mögliche Alternative dar, die eine weitere Verbesserung der Kapazität ermöglicht. Das Material besitzt eine deutlich höhere Permittivität und eine ausreichend große Bandlücke. Diese Arbeit beschäftigt sich deshalb mit Herstellung und detaillierter physikalischer und elektrischer Charakterisierung von extrem dünnen CaTiO3 Schichten. Zusätzlich wurden diverse Elektroden bezüglich ihrer Temperaturstabilität und der chemischen Stabilität untersucht, um kristallines CaTiO3 zu herhalten. Als eine optimale Elektrode stellte sich Pt auf TiN heraus. Physikalische Experimente an extrem dünnen CaTiO3 Schichten bestätigen die Bandlücke von 4,0-4,2 eV. Wachstumsuntersuchungen an kristallinem CaTiO3 zeigen eine Reduktion der Kristallisationstemperatur von 640°C auf SiO2 zu 550°C auf Pt. Diese Reduktion wurde detailliert mittels Transmissionselektronenmikroskopie untersucht. Es konnte für einige Schichten ein partielles lokales epitaktischesWachstum von (111) CaTiO3 auf (111) Pt gemessen werden. Dieses Vorzugswachstum ist vorteilhaft für die elektrischen Eigenschaften durch eine gesteigerte Permittivität von 55 bei gleichzeitig geringem Leckstrom vergleichbar zu amorphen Schichten. Eine genaue elektrische Analyse von Kondensatoren mit amorphen und kristallinem CaTiO3 ergibt eine Permittivität von 30 für amorphe und bis zu 105 für kristalline CaTiO3 Schichten. Die Permittivität zeigt eine quadratische Abhängigheit von der angelegten Spannung. Kristallines CaTiO3 zeigt einen 1-3% Abfall der Permittivität bei 1V, der wesentlich geringer ausfällt als vergleichbare Werte für SrTiO3. Eine zu SiO2 vergleichbare Schichtdicke (CET) von unter 1,0 nm mit Stromdichten von 1×10−8 A/cm2 wurde auf Kohlenstoffsubstraten erreicht. Mit Werten von 0,5 nm bei Leckstromdichten von 1×10−7 A/cm2 auf Pt/TiN Elektroden erfüllen die CaTiO3 Kondensatoren die Anforderungen der ITRS Strategiepläne für Arbeitsspeicher ab 2016

Photopatternable gate insulator for oxide TFTs

A photopatternable and solution-processable dielectric polymer, as the one provided by Solvay for this work, has physical properties that make it a unique candidate for gate dielectric in thin-film transistors (TFT), allowing to save time and reduce the complexity of the processes involved. To demonstrate that this material can be patterned using Ultra-Violet (UV) light and the exposed pattern can be developed in acetone, an opti-mization of the processing conditions was made in terms of the deposition conditions, curing and development steps. The polymer films were deposited by spin coating, followed by a baking at 90°C for 10 minutes and cured using a lightbulb with 365nm wavelength. The films were then characterized by profilometry, transmit-tance, atomic force microscopy (AFM), and scanning electron microscopy/energy dispersive spectroscopy (SEM/EDS). The polymer films were used in metal-insulator-metal (MIM) capacitors as well as gate dielectric in In-Ga-Zn-O (IGZO) TFTs. The MIM capacitors showed a dielectric constant of 8.35 at 1kHz, a leakage current density below 1.07×10-7 A.cm-2 at 1MV.cm-1, and a breakdown field higher than 1.5MV.cm-1. The TFT had turn-on voltage (Von) of -1V, saturation mobility of (μSat) of 7.07 cm2·V-1·s-1 and on/off current ratio of 105, positioning them close to the IGZO TFTs using traditional dielectrics that require complex etching processes.Um polímero foto padronizável, como o fornecido pela Solvay, é um polímero dielétrico com proprie-dades físicas que fazem dele um excelente candidato para ser utilizado no fabrico de um transístor de filme fino (TFT), permitindo poupar tempo e reduzir a complexidade dos processos. Com o objetivo de demonstrar que este material consegue ser padronizado utilizando luz UV e revelando o padrão em acetona, foi feita uma otimização das condições não só da deposição deste filme, bem como do processo de cura e revelação do mesmo, de forma a tentar manter as suas propriedades dielétricas. Os filmes foram depositados por spincoa-ting, seguido de um baking a 90° C por 10 minutos e curados utilizando uma lâmpada com comprimento de onda de 365nm. Os filmes foram caracterizados através de medidas de perfilometria, transmitância, microsco-pia de força atómica e microscópio de varrimento eletrónico e espetroscopia de energia dispersiva de raio-x (SEM/EDS). Os filmes foram também depositados em estruturas metal isolante metal (MIM) e como dielétrico de porta em transístores de filme fino de In-Ga-Zn-O (IGZO) produzidos em duas arquiteturas diferentes. Os condensadores MIM exibiram uma constante dielétrica de 8.35 a 1kHz, uma densidade de corrente de fuga de cerca de 2.21x10-12 A.cm-2 a 1MV.cm-1 e um campo elétrico de rutura superior a 3 MV.cm-1. Os TFTs produ-zidos, exibiram uma tensão on (Von) de -1V, uma mobilidade de efeito de campo (μFE) de 7.07 cm2·V-1·s-1 e uma razão de corrente on/off de 105, colocando estes dispositivos perto de valores apresentados em TFTs de IGZO que usam dielétricos tradicionais e são produzidos por técnicas complexas de etching

Fabrication and nano-scale characterisation of ferroelectric thin films

PhD ThesisThis thesis focuses on the fabrication and characterisation of BaTiO3 thin films. One of the aims is to deposit amorphous BaTiO3 films on conductive thin films through sputtering at temperatures compatible with semiconductor manufacturing, followed by post deposition annealing to crystallise these films. However, rapid thermal processing (RTP) is known to create pinholes and cracks due to thermal mismatches between the electrode and insulator, causing degradation of the film quality. Initial focus was to develop thin film electrodes which can withstand process temperatures above 800 C. Deposition conditions, including the nitrogen flow rate relative to that of argon during deposition were optimised to obtain TiNx with least resistivity and excellent material properties through reactive sputtering. TiNx films deposited at various nitrogen flow rates were then annealed in a non-oxidising condition and their properties were thoroughly studied. Films deposited at the highest nitrogen flow rate (95%) showed least variation in resistivity and showed excellent material properties even after a high temperature anneal. BaTiO3 films of varying thicknesses were deposited on TiNx using RF-sputtering and subjected to RTP at various temperatures. It was found that there exists a critical thickness for each RTP temperature below which BaTiO3 films are pinhole free. A process was then developed by depositing and annealing multiple layers of BaTiO3 films, with the thickness of each deposition less than the critical thickness. It was observed that the multi-layered films are stable and pinhole free with a smooth surface while the single layers of equivalent thicknesses showed cracked surfaces. Current-atomic force microscopy studies showed leakage current through large pinholes in single-layered films, whereas the pinholes were not the leakage path for multi-layered films. Metal-insulator-metal capacitor structures were also fabricated using BaTiO3 with TiNx top and bottom electrodes and the fringing effects in leakage characteristics were studied. Finally, the polarisation reversal mechanism in BaTiO3 was investigated using piezoresponse force spectroscopy (PFS). It was experimentally demonstrated that the polarisation reversal in these materials is a two-step process, which involves polarisation rotation and switching when the applied electric field is not parallel to the crystallographic orientation of the grain. However, it is a single step switching when the polarisation and the electric field are parallel, as widely perceived. The two step polarisation reversal was found to help [101] and [111] oriented grains to switch at a lower electric field compared to [001] grains.Engineering and Physical Sciences Research Council (EPSRC), UK: Intel Ireland

TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Fabrication and characteristics of high-k MIM capacitors for high precision applications

Ph.DDOCTOR OF PHILOSOPH

Leakage current and resistive switching mechanisms in SrTiO3

PhD ThesisResistive switching random access memory devices have attracted considerable attention due to exhibiting fast programming, non-destructive readout, low power-consumption, high-density integration, and low fabrication-cost. Resistive switching has been observed in a wide range of materials but the underpinning mechanisms still have not been understood completely. This thesis presents a study of the leakage current and resistive switching mechanisms of SrTiO3 metal-insulator-metal devices fabricated using atomic layer deposition and pulse laser deposition techniques. First, the conduction mechanisms in SrTiO3 are investigated. The leakage current characteristics are highly sensitive to the polarity and magnitude of applied voltage bias, punctuated by sharp increases at high field. The characteristics are also asymmetric with bias and the negative to positive current crossover point always occurs at a negative voltage bias. A model comprising thermionic field emission and tunnelling phenomena is proposed to explain ii the dependence of leakage current upon the device parameters quantitatively. SrTiO3 also demonstrates bipolar switching behaviour where the current-density versus voltage (J-V) characteristics show asymmetry at all temperatures examined, with resistive switching behaviour observed at elevated temperatures. The asymmetry is explained by the relative lack of electron traps at one electrode, which is determined from the symmetric J-V curve obtained at room temperature due to the redistribution of the dominant electrical defects in the film. Evidence is presented for a model of resistive switching that originates from defect diffusion (possibly oxygen vacancies) at high temperatures. Finally, a peculiar resistive switching behaviour was observed in pulse laser deposited SrTiO3. This switching depends on both the amplitude and polarity of the applied voltage, and cannot be described as either bipolar or unipolar resistive switching. This behaviour is termed antipolar due to the opposite polarity of the set voltage relative to the previous reset voltage. The proposed model based on electron injection by tunnelling at interfaces and a Poole-Frenkel mechanism through the bulk is extended to explain the antipolar resistive switching behaviour. This model is quantified by use of a simple mathematical equation to simulate the experimental results

Lanthanoid based materials in advanced CMOS technology

Ph.DDOCTOR OF PHILOSOPH