The development of sub-25 nm III-V High Electron Mobility Transistors

High Electron Mobility Transistors (HEMTs) are crucially important devices in microwave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecommunications applications operating at frequencies well above 100 GHz. These new applications have driven demand for high frequency, low noise device operation; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance. Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years. This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam lithography and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described. This work has led to the successful fabrication of functional 22 nm HEMTs and the development of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes

Gallium Arsenide Based Metal-Semiconductor-Metal Devices and Detectors

Each year the creation and refinement of new material growth techniques give rise to novel material systems for electronic device exploration. A metal-semiconductor-metal (MSM) device is the simplest electronic device possible, consisting of two metal contacts on a semiconducting channel. Despite their simplicity, these devices can operate as high performance detectors as well as enable rapid characterization of novel electronic materials. This thesis will discuss the fabrication and characterization of MSM devices on a two-dimensional electron hole gas (2DEHG) and GaAs-based nanowires. 2DEHG structures consist of two spatial separated quantum wells of opposite charge. These devices exhibit a high-speed photo-response, a two plateau varactor response and give rise to several unexplained photoluminescence peaks. GaAs-based nanowire MSMs offer the opportunity to fabricate many of the well known bulk III-V semiconductor devices on the nanoscale. Accomplishing this requires quality ohmic contacts. Several fabrication methods to create ohmic contacts on GaAs nanowires are described, as well as characterization of the light response of these devices and results demonstrating ambipolar transport in a wide bandgap material. The devices offer promise as high speed on-chip interconnects for digital circuits.Ph.D., Electrical Engineering -- Drexel University, 201

Design, Growth, and Characterization of III-Sb and III-N Materials for Photovoltaic Applications

abstract: Photovoltaic (PV) energy has shown tremendous improvements in the past few decades showing great promises for future sustainable energy sources. Among all PV energy sources, III-V-based solar cells have demonstrated the highest efficiencies. This dissertation investigates the two different III-V solar cells with low (III-antimonide) and high (III-nitride) bandgaps. III-antimonide semiconductors, particularly aluminum (indium) gallium antimonide alloys, with relatively low bandgaps, are promising candidates for the absorption of long wavelength photons and thermophotovoltaic applications. GaSb and its alloys can be grown metamorphically on non-native substrates such as GaAs allowing for the understanding of different multijunction solar cell designs. The work in this dissertation presents the molecular beam epitaxy growth, crystal quality, and device performance of AlxGa1−xSb solar cells grown on GaAs substrates. The motivation is on the optimization of the growth of AlxGa1−xSb on GaAs (001) substrates to decrease the threading dislocation density resulting from the significant lattice mismatch between GaSb and GaAs. GaSb, Al0.15Ga0.85Sb, and Al0.5Ga0.5Sb cells grown on GaAs substrates demonstrate open-circuit voltages of 0.16, 0.17, and 0.35 V, respectively. In addition, a detailed study is presented to demonstrate the temperature dependence of (Al)GaSb PV cells. III-nitride semiconductors are promising candidates for high-efficiency solar cells due to their inherent properties and pre-existing infrastructures that can be used as a leverage to improve future nitride-based solar cells. However, to unleash the full potential of III-nitride alloys for PV and PV-thermal (PVT) applications, significant progress in growth, design, and device fabrication are required. In this dissertation, first, the performance of ii InGaN solar cells designed for high temperature application (such as PVT) are presented showing robust cell performance up to 600 ⁰C with no significant degradation. In the final section, extremely low-resistance GaN-based tunnel junctions with different structures are demonstrated showing highly efficient tunneling characteristics with negative differential resistance (NDR). To improve the efficiency of optoelectronic devices such as UV emitters the first AlGaN tunnel diode with Zener characteristic is presented. Finally, enabled by GaN tunnel junction, the first tunnel contacted InGaN solar cell with a high VOC value of 2.22 V is demonstrated.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Effect of varying gate-drain distance on the RF power performance of pseudomorphic high electron mobility transistors

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 134-137).AIGaAs/lnGaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) are widely used in satellite communications, military and commercial radar, cellular telephones, and other RF power applications. One key figure of merit in these applications is RF power output. Increasing the gate-to-drain length (LRD) of the PHEMT leads to an increase in its breakdown voltage. This should theoretically allow the selection of a higher drain operating voltage and consequently result in higher output power at microwave frequencies. However, experimentally, a decrease in output power and peak power-added efficiency is generally observed with increasing LRD In order to understand this, we have studied in detail the RF power performance of industrial PHEMTs with different values of LRD. We have found that there is an optimum value of LRD beyond which the maximum RF power output that the device can deliver drops. In addition, we have found that the output power of long LRD devices declines significantly with increasing frequency. We explain the difference in RF power behavior of the different devices through the evolution of load lines with frequency, LRD, and operating voltage. We have found that the presence of oscillations in the NDR region limit the maximum allowable operating voltage of long LRD devices through catastrophic burnout. The maximum voltage of short LRD devices is limited by electrical degradation. Pulsed I-V measurements have revealed that long LRD devices increasingly suffer from surface state activity that limit the maximum drain current under RF operation. A delay time analysis has shown an increasing extension of the depletion region toward the drain with increasing LRD that limits the frequency response of long LRD devices.by Melinda F. Wong.S.M

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of Inx≥0.53Ga1-xAs/In0.52Al0.48As and Inx≥0.1Ga1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm2/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In0.85Ga0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (Lside) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH4)2S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al2O3/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×1012cm-2eV-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (Id,sat=1.14mA/mm), double peaked transconductance (gm=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (Ron=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of Id,sat (11×), gm (5.5×) and Ron (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (Lside) from 1μm down to 70nm improved Id,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In0.3Ga0.7Sb-channel (Id,sat=49.4mA/mm, gm=12.3mS/mm, Ron=31.7kΩ.μm) and In0.4Ga0.6Sb-channel (Id,sat=38mA/mm, gm=11.9mS/mm, Ron=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS

Silicon Nanodevices

This book is a collection of scientific articles which brings research in Si nanodevices, device processing, and materials. The content is oriented to optoelectronics with a core in electronics and photonics. The issue of current technology developments in the nanodevices towards 3D integration and an emerging of the electronics and photonics as an ultimate goal in nanotechnology in the future is presented. The book contains a few review articles to update the knowledge in Si-based devices and followed by processing of advanced nano-scale transistors. Furthermore, material growth and manufacturing of several types of devices are presented. The subjects are carefully chosen to critically cover the scientific issues for scientists and doctoral students