Design methodology for a maximum sequence length MASH digital delta-sigma modulator

The paper proposes a novel structure for a MASH digital delta-sigma modulator (DDSM) in order to achieve a long sequence length. The expression for the sequence length is derived. The condition to produce the maximum sequence length is also stated. It is proved that the modulator output only depends on the structure of the first-order error feedback modulator (EFM1) which is the first stage of a Multi-stAge noise SHaping (MASH) modulator

Global stability, limit cycles and chaotic behaviors of second order interpolative sigma delta modulators

It is well known that second order lowpass interpolative sigma delta modulators (SDMs) may suffer from instability and limit cycle problems when the magnitudes of the input signals are at large and at intermediate levels, respectively. In order to solve these problems, we propose to replace the second order lowpass interpolative SDMs to a specific class of second order bandpass interpolative SDMs with the natural frequencies of the loop filters very close to zero. The global stability property of this class of second order bandpass interpolative SDMs is characterized and some interesting phenomena are discussed. Besides, conditions for the occurrence of limit cycle and fractal behaviors are also derived, so that these unwanted behaviors will not happen or can be avoided. Moreover, it is found that these bandpass SDMs may exhibit irregular and conical-like chaotic patterns on the phase plane. By utilizing these chaotic behaviors, these bandpass SDMs can achieve higher signal-to-noise ratio (SNR) and tonal suppression than those of the original lowpass SDMs

A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW

Estimation of an initial condition of sigma-delta modulators via projection onto convex sets

Abstract—In this paper, an initial condition of strictly causal rational interpolative sigma-delta modulators (SDMs) is estimated based on quantizer output bit streams and an input signal. A set of initial conditions generating bounded trajectories is characterized. It is found that a set of initial conditions generating bounded trajectories but not necessarily corresponding to quantizer output bit streams is convex. Also, it is found that a set of initial conditions corresponding to quantizer output bit streams but not necessarily generating bounded trajectories is convex too. Moreover, it is found that an initial condition both corresponding to quantizer output bit streams and generating bounded trajectories is uniquely defined if the loop filter is unstable (Here, an unstable loop filter refers to that with at least one of its poles being strictly outside the unit circle). To estimate that unique initial condition, a projection onto convex set approach is employed. Numerical computer simulations show that the employed method can estimate the initial condition effectively

A method for searching the limit cycles of high order Sigma-Delta modulators

In this paper an approach for description and validation of potential limit cycles of high order sigma-delta modulators is presented. The approach is based on a parallel decomposition of the modulator. In this representation, the general N-th order modulator is transformed into a decomposition of low order, generally complex modulators, which interact only through the quantizer function. The decomposition considered helps to describe easily the time domain behavior of the modulator. Based on this, the conditions for the existence of limit cycles in the high order modulator for constant inputs, are obtained. They are determined by the periodicity conditions for the states of the first order modulators. In this case, the state variables are uncoupled and the obtained conditions are very easy to be checked. Limit cycles correspond to periodic output sequences and the proposed method includes description and validation of possible sequences

Components for oversampled signal processors

Oversampled converters trade transmission bandwidth for resolution. An idealized model gives an insight into the way in which signals are encoded and thus how they can be manipulated. Oversampling offers a form of signal processing that requires simple processing elements capable of exploiting the growing clock speeds available in integrated solutions. Simultaneously avoids the need for analog circuitry. This paper reviews common operations that can be performed on oversampled signals

DC stability analysis of high-order, lowpass ΣΔ modulators with distinct unit circle NTF zeros

This paper presents an analytical approach to the investigation of the dc stability of high-order (order > 2), low-pass (LP) ΣΔ modulators with distinct noise transfer function (NTF) zeros on the unit circle. The techniques of state-space diagonalization and decomposition, continuous-time embedding and Poincaré map analysis are combined and extended. It is revealed that high-order ΣΔ modulators can be transformed and decomposed into second- and first-order subsystems. The investigation, coupled with efficient numerical methods, generalizes itself to different types of transition flow and provides theoretical insight into the state trajectory and limit cycle behavior. It is shown that estimation of dc input bounds based solely on the boundary transition flow is inadequate. A procedure utilizing the information from different transition flow assumptions and the discrete nature of a modulator is introduced for locating the stable dc input bounds of practical, discrete-time ΣΔ modulators.published_or_final_versio

Mathematical analysis of prime modulus quantizer MASH digital delta-sigma modulator

A MASH digital delta-sigma modulator (DDSM) is analyzed mathematically. It incorporates first-order error feedback modulators (EFM) which include prime modulus quantizers to guarantee a minimum sequence length M. The purpose of this analysis is to calculate the exact sequence length of the aforementioned MASH DDSM. We show that the sequence length for an lth-order member of this modulator family is M for all constant inputs, and for all initial conditions, where M is the sequence length of the constituent first-order prime modulus quantizer EFMs.