A low power bandgap voltage reference for low-dropout regulator

A low power Bandgap Voltage Reference (BGR) is designed to supply a voltage reference for a low voltage Low-Dropout Regulator (LDO). This bandgap design consists of a bandgap core circuit, an output stage and a start-up circuit. The output of the bandgap adopted sub-1V voltage reference through the output stage circuit. The bandgap is simulated using 0.13 μm CMOS process. This BGR circuit provides voltage reference of 64mV± 1mV over-25°C to 120°C temperature range. The power supply of this BGR circuit is 1.20 V and the total current is 20 μA, thus resulting a low total power consumption of 24μW. The total layout area for this bandgap design is 66μm × 100μm

A Low-Power Low-Voltage Bandgap Reference in CMOS

Bandgap reference plays a substantial role in integrated circuit. Traditionally, it provides a constant reference voltage of 1.2051/ for other blocks in the circuit while itself is independent of temperature and power supply. However, the development of CMOS technology has brought us into a new era of high integration and ultra-low power consumption. As the gate length scales down, it is crucial to build circuits that are able to work under a very low voltage power supply, for instance, lower than the bandgap voltage of 1.205V. Building bandgap circuits to generate the conven­ tional bandgap voltage under a low voltage power supply such as 1.2V or IV is no longer practical nor useful. Thus, bandgap references working under low-voltage and consuming low-power is becoming the trend of research and development nowadays. In this thesis work, the potential structure of a low-voltage low-power bandgap reference is proposed, which is based on extracting a current that is a fraction of the traditional bandgap voltage. All the necessary blocks are designed to achieve the high accuracy bandgap reference, including bandgap core circuit, op-amp, start-up circuit and output stage. As a result, the designed bandgap reference is able to work under 1.2V power supply and provides an output reference voltage of 584.7mV. It has a variation of only 244.38fiV for the temperature range of 0°C ~ 125°C and has a variation of only 1.1mV for a power supply range of 1.08V ~ 1.32V. The layout design for the bandgap reference structure is also done carefully at the late stage, with an area of 100fj,m x 85¡xm

A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility

Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from −55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420 nA at 27°C

A 0.6V improved PSRR bandgap reference for power management system in RF energy harvesting applications

The scaling of technology to lower process nodes is a major convenience as it allows for power saving by allowing the circuit to operate at a lower voltage. As per the prediction by International Technology Roadmap for Semiconductors (ITRS), the supply voltage will reduce down to 0.4V by 2024. Although the reduction of supply voltage is favourable in terms of power-saving, especially in powering Internet of Things (IoT) devices, the penalty incurred by this is the degradation of power supply rejection ratio (PSRR) due to reduced output impedance of bandgap reference circuits at lower voltage supply. The proposed work aims to mitigate this problem by employing metal oxide semiconductors (MOS) based proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generator and regulated cascode techniques to improve the PSRR even at lower voltage supply, eliminating the need for voltage doubler circuits which injects noise in the substrate and degrades circuit performance. This improved PSRR bandgap reference circuit will then be used to power-up circuits that require high PSRR and clean power supply to ensure optimal functionality of IoT circuits, particularly sensitive circuits that degrade in functionality when subjected to noise travelling through power supply such as low power sensors and voltage controlled oscillators (VCOs) in frequency synthesizers. The objectives of this work are to investigate the characteristics and performances of the power management unit for radio frequency energy harvesting (RFEH) applications, design and develop bandgap reference with improved PSRR at low voltage supply, design and develop a low dropout (LDO) regulator to provide a constant voltage reference in RFEH system and validate and analyze the performance of the proposed circuit. This work managed to achieve a reference voltage of 0.405V over a wide temperature of -40 to 125˚C, a PSRR of -41dB, line and load regulation of 1.188mV/V and 2.506mV/mA respectively and load current range from 0 to 800µA. The current consumption of the bandgap is 20.33µA and the whole power management unit (PMU) is 37µA and the temperature coefficient (TC) is 64.41ppm/˚C. The bandgap area is 0.0627mm2 while the whole PMU is 0.142mm2. Overall, the design passes all the post layout validations such as design rule check (DRC) and layout vs schematic (LVS) and functions as expected. The post-layout simulations were analyzed and the results closely agree with the pre-layout simulations. On top of that, this work demonstrates the robustness of the bandgap reference circuit when integrated at the top level with the LDO, start-up and biasing circuits as it is able to operate, with 50% improvement in PSRR over conventional design at a supply voltage of 0.6V, making it suitable to power up sensitive IoT circuits

Embedded 5V-to-3.3V Voltage Regulator for Supplying Digital ICs in 3.3V CMOS Technology

A fully integrated 5 V-to-3.3 V supply voltage regulator for application in digital IC's has been designed in a 3.3 V 0.5 μm CMOS process. The regulator is able to deliver peak current transients of 300 mA, while the output voltage remains within a margin of 10% around the nominal value. The circuit draw's a static quiescent current of 750 μA during normal operation, and includes a power-down mode with only 10 μA current consumption. The die area is 1 mm2, and can be scaled proportional to the maximum peak current. Special precautions have been taken to allow 5 V in the 3.3 V process

A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value

Implementation of a Low Power CMOS Ban dgap Voltage Reference Source

运用带隙基准的原理,提出了一种带启动电路的低功耗带隙基准电压源电路。HSPICE仿真结果表明,在25℃3、.3 V下,电路功耗为16.88μW;另外,在-30~125℃范围内,1.9~5.5V下,输出基准电压VREF=1.225±0.0015 V,温度系数为γTC=14.75×10-6/℃,电源电压抑制比(PSRR)为86 dB。该电路采用台积电(TSMC)0.35μm 3.3 V/5 V CMOS工艺制造。测试结果显示,电路功耗仅为16.98μW。A low power CMOS bandgap voltage reference source with a start-up circuit is presented based on the bandgap voltage theory.Results from Hspice simulation show that power dissipation of the circuit is 16.88 μW at 3.3 V and 25 ℃.The voltage reference has an output voltage of 1.225 ±0.0015 V for a temperature coefficient of 14.75×10-6/℃,and a PSRR of 86 dB in the temperature range from-30 ℃ to 125 ℃ and VDD from 1.9 V to 5.5 V.This circuit is fabricated using TSMC's 0.35 μm(3.3 V/5 V) CMOS technology,which consumes 16.98 μW of power from a single 3.3 V power supply.福建省自然科学基金资助项目(2002H020

The Intermediate Band Solar Cell: Progress Toward the Realization of an Attractive Concept

The intermediate band (IB) solar cell has been proposed to increase the current of solar cells while at the same time preserving the output voltage in order to produce an efficiency that ideally is above the limit established by Shockley and Queisser in 1961. The concept is described and the present realizations and acquired understanding are explained. Quantum dots are used to make the cells but the efficiencies that have been achieved so far are not yet satisfactory. Possible ways to overcome the issues involved are depicted. Alternatively, and against early predictions, IB alloys have been prepared and cells that undoubtedly display the IB behavior have been fabricated, although their efficiency is still low. Full development of this concept is not trivial but it is expected that once the development of IB solar cells is fully mastered, IB solar cells should be able to operate in tandem in concentrators with very high efficiencies or as thin cells at low cost with efficiencies above the present ones

A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2