Yet Another Compressed Cache: a Low Cost Yet Effective Compressed Cache

Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps between cores and off-chip memory. However, caches frequently consume a significant fraction of a multicore chip’s area, and thus account for a significant fraction of its cost. Compression has the potential to improve the effective capacity of a cache, providing the performance and energy benefits of a larger cache while using less area. The design of a compressed cache must address two important issues: i) a low-latency, low-overhead compression algorithm that can represent a fixed-size cache block using fewer bits and ii) a cache organization that can efficiently store the resulting variable-size compressed blocks. This paper focuses on the latter issue. In this paper, we propose YACC (Yet Another Compressed Cache), a new compressed cache design that uses super-blocks to reduce tag overheads and variable-size blocks to reduce internal fragmentation, but eliminates two major sources of complexity in previous work—decoupled tag-data mapping and address skewing. YACC’s cache layout is similar to conventional caches, eliminating the back-pointers used to maintain a decoupled tag-data mapping and the extra decoders used to implement skewed associativity. An additional advantage of YACC is that it enables modern replacement mechanisms, such as RRIP. For our benchmark set, YACC performs comparably to the recently-proposed Skewed Compressed Cache (SCC) ‎[Sardashti et al. 2014], but with a simpler, more area efficient design without the complexity and overheads of skewing. Compared to a conventional uncompressed 8MB LLC, YACC improves performance by on average 8% and up to 26%, and reduces total energy by on average 6% and up to 20%. An 8MB YACC achieves approximately the same performance and energy improvements as a 16MB conventional cache at a much smaller silicon footprint, with 1.6% higher area than an 8MB conventional cach

Performance Improvements Using Dynamic Performance Stubs

This thesis proposes a new methodology to extend the software performance engineering process. Common performance measurement and tuning principles mainly target to improve the software function itself. Hereby, the application source code is studied and improved independently of the overall system performance behavior. Moreover, the optimization of the software function has to be done without an estimation of the expected optimization gain. This often leads to an under- or overoptimization, and hence, does not utilize the system sufficiently. The proposed performance improvement methodology and framework, called dynamic performance stubs, improves the before mentioned insufficiencies by evaluating the overall system performance improvement. This is achieved by simulating the performance behavior of the original software functionality depending on an adjustable optimization level prior to the real optimization. So, it enables the software performance analyst to determine the systems’ overall performance behavior considering possible outcomes of different improvement approaches. Moreover, by using the dynamic performance stubs methodology, a cost-benefit analysis of different optimizations regarding the performance behavior can be done. The approach of the dynamic performance stubs is to replace the software bottleneck by a stub. This stub combines the simulation of the software functionality with the possibility to adjust the performance behavior depending on one or more different performance aspects of the replaced software function. A general methodology for using dynamic performance stubs as well as several methodologies for simulating different performance aspects is discussed. Finally, several case studies to show the application and usability of the dynamic performance stubs approach are presented

The Effects of Microprocessor Architecture on Speedup in Distrbuted Memory Supercomputers

Amdahl\u27s Law states that speedup in moving from one processor to N identical processors can never be greater than N, and in fact usually is lower than N because of operations that must be done sequentially. Amdahl\u27s Law gives us the following formula for speedup: Speedup \u3c or = (S+P)/(S+(P/N)) where is the number of processors, S is the percentage of the code that is serial (i.e., cannot be parallelized), and P is the percentage of code that is parallelizable. We can substitute 1 - S for P in the above formula and we see that as S approaches zero speedup approaches N. It can also be shown that seemingly small values of S can severely limit the maximum speedup. Researchers at the University of Maine saw speedups that seemed to contradict Amdahl\u27s Law, and identified an assumption made by the law that is not always true. When this assumption is not true, it is possible to achieve speedups that are larger than the theoretical maximum speedup of N given by Amdahl\u27s Law. The assumption in question is that the computer performance scales linearly as the size of the problem is reduced by dividing it over a larger number of processors. This assumption is not valid for computers with tiered memory. In this thesis we investigate superlinear speedup through a series of test programs specifically designed to exhibit superlinear speedup. After demonstrating these programs show superlinear speedup, we suggest methods for detecting the potential for superlinear speedup in a variety of algorithms

Improving the SLLC Efficiency by exploiting reuse locality and adjusting prefetch

Desde los teléfonos móviles inteligentes hasta nuestro ordenador portátil los sistemas electrónicos que incluyen chips multiprocesador (CMP) están presentes en nuestra vida cotidiana de una manera abrumadora. Los CMPs contienen varios núcleos o CPUs que tienen que ser alimentados con datos provenientes de la memoria. Pero la velocidad a la que los núcleos que forman el CMP necesitan los datos es mucho mayor que la velocidad a la que la memoria es capaz de proporcionar dichos datos. De hecho, esta diferencia ha ido aumentando desde prácticamente el día en el que ambos dispositivos fueron concebidos. Esta diferencia en el rendimiento de ambos dispositivos se ha venido a llamar "the memory gap". Al mismo tiempo que dicha diferencia aumentaba, los lenguajes de programación proporcionaban a los programadores modelos de memoria que podían acceder a un espacio prácticamente infinito y al que, además, se accedía de manera instantánea. Pero el tamaño de cualquier estructura hardware está íntimamente relacionado con su tiempo de acceso y éste será mayor cuanto mayor sea el tamaño la estructura hardware a acceder. Con el ánimo de deshacer esta aparente contradicción, los arquitectos de computadores incluyeron memorias intermedias entre las CPUs y la grande, aunque al mismo tiempo lenta, memoria principal. Estas memorias intermedias se denominan memorias cache o simplemente caches. Debido a la gran diferencia que existe entre la velocidad del procesador y la de la memoria principal. Los CMPs en la actualidad están provistos de una jerarquía de memorias cache que tiene dos o tres niveles. Las caches que están cerca del procesador sólo contienen unos pocos kilobytes (entre 4 y 64) accesibles en uno o pocos ciclos de reloj, mientras que las que se encuentran más alejadas del procesador pueden llegar a contener varios megabytes y tener un tiempo de acceso de varias decenas de ciclos. Los programas al ser ejecutados muestran una propiedad llamada localidad que se expresa en los ejes espacial y temporal. La localidad temporal es la propiedad que dice que el programa volverá a usar datos que usó recientemente, cuanto más recientemente los usó, más probable es que vuelva a hacerlo. Mientras que la localidad espacial es la propiedad que dice que el programa tenderá a usar datos que están próximos en el espacio de memoria a datos que usó recientemente. Las memorias cache han sido diseñadas tradicionalmente para explotar la localidad. En concreto, la localidad temporal se explotaba mediante una adecuada política de reemplazo, mientras que la localidad espacial se explota al contener cada bloque de cache varios datos o palabras. Un modo adicional de conseguir explotar una mayor cantidad de localidad espacial es mediante el uso de la técnica llamada prebúsqueda. La política de reemplazo influye de manera crítica en la tasa de aciertos de la memoria cache. En un CMP provisto de una jerarquía de memorias cache, la localidad temporal se explota en aquellos niveles más cercanos a los núcleos. Así que muchos de los bloques insertados en la SLLC son de un solo uso, es decir, estos bloques no experimentarán ningún acierto más durante todo el tiempo que permanezcan en la SLLC. Sin embargo, aquellos bloques que lleguen a experimentar un acierto en la SLLC, normalmente experimentarán muchos más aciertos. Por lo tanto, que la política de reemplazo base sus decisiones en la posible explotación de la localidad temporal, es una asunción inválida cuando hablamos de la SLLC. Por el contrario, Este comportamiento indica que dicha política de reemplazo de la SLLC debería estar basada en el reúso1 en lugar de en la localidad temporal. La prebúsqueda hardware tiene por objetivo cargar en la cache datos antes de que sea el procesador quien los pida. La validez de esta técnica a la hora de reducir la latencia media de acceso a memoria ha sido ampliamente demostrada. La prebúsqueda funciona especialmente bien en las jerarquías de memoria de sistemas monoprocesador, donde solamente hay un flujo de datos entre el procesador y la memoria. Sin embargo, cuando la prebúsqueda se usa en un sistema multiprocesador donde diferentes aplicaciones se están ejecutando al mismo tiempo, las prebúsquedas asociadas a un núcleo podrían interferir con los datos cargados en la cache por otro núcleo, provocando la eliminación de los contenidos de otra aplicación y dañando su rendimiento. Es necesario por tanto un mecanismo para regular la prebúsqueda asociada a cada uno de los núcleos. Este mecanismo debería tener por objetivo el mejorar el rendimiento general del sistema. 1 Aunque el DRAE no contenga su definición, usaremos aquí el verbo reusar (así como sus formas derivadas) como sinónimo de volver a utilizar. Cada fallo en la SLLC provoca un acceso a la memoria principal que se encuentra fuera del chip. Además la memoria principal está hecha de chips de DRAM. Ambos factores incrementan su latencia de acceso, latencia que se suma a cada uno de los accesos que falla en la SLLC, penalizando a la vez la latencia media de acceso a memoria. Por lo tanto, la tasa de aciertos de la SLLC es un factor crítico para lograr una latencia media de acceso a memoria óptima. Esta tesis fija su atención en la eficiencia de los dos aspectos comentados con anterioridad: la eficiencia de la prebúsqueda y la eficiencia de la política de reemplazo. Las contribuciones principales de esta tesis son las siguientes: 1) Enunciamos una propiedad llamada localidad de reúso que dice que i) los bloques de cache que hayan sido usados más de una vez tienen una alta probabilidad de ser usados muchas veces en el futuro. ii) Los bloques de cache recientemente reusados son más útiles que otros reúsados previamente. Defendemos en esta tesis que el patrón de acceso a la SLLC muestra localidad de reúso. 2) En esta tesis se proponen dos algoritmos de reemplazo capaces de explotar la localidad de reúso, Least-recently reused (LRR) y Not-recently reused (NRR). Estos dos nuevos algoritmos son modificaciones de otros dos muy bien conocidos: Least-recently used (LRU) y Not-recently used (NRU). Dichos algoritmos fueron diseñados para explotar la localidad temporal, mientras que los nuestros explotan la local- idad de reúso. Las modificaciones propuestas no suponen ninguna sobrecarga hardware respecto a los algoritmos base. Durante esta tesis se muestra que nuestros algoritmos mejoran consistentemente el rendimiento de los originales. 3) Proponemos un novedoso diseño para la SLLC llamado Reuse Cache. En este diseño los arrays de etiquetas y datos de la cache están desacoplados. Solamente se almacenan en el array de datos aquellos bloques que hayan mostrado reúso. El array de etiquetas se usa para detectar reúso y mantener la coherencia. Esta estructura permite reducir el tamaño del array de datos de manera drástica. Como ejemplo, una Reuse Cache con un array de etiquetas equivalente al de una cache convencional de 4MB y un array de datos de 1MB, tiene el mismo rendimiento medio que una cache convencional de 8MB, pero con un ahorro de almacenamiento de en torno al 84%. 4) Un controlador de bajo coste llamado ABS capaz de ajustar la agresividad de la prebúsqueda asociada a cada uno de los núcleos de un CMP pero con el ánimo de mejorar el rendimiento general del sistema. El controlador funciona de manera aislada en cada uno de los bancos de la SLLC y recoge métricas locales. Para optimizar el rendimiento global del sistema busca la combinación óptima de valores de la agresividad de prebúsqueda. Para inferir cuál es esa combinación óptima usa una estrategia de búsqueda hill-climbing

Ethical business modeling: developing a business model for the REIT industry towards an ethical structure

This research explores the development and validity of a questioning framework to better understand the Real Estate Investment Trust (REIT) business model. This framework will equip investors to navigate the rough seas of public equity investing. As an equity research analyst with two decades of experience, I aspire to enhance the level of investor education across Asia Pacific. With better investor education, the degree of information asymmetry between retail investors and financial institutions will reduce, leading to improvement in market integrity. This research has been initiated in the context of taxpayers underwriting losses sustained by numerous too-big-to-fail companies with unsustainable business models partially due to unconstrained quantitative easing conducted by central bankers. Together with institutionally orchestrated pump-and-dump strategies, unsuspecting retail investors often find themselves at the receiving end during the eventual equity market debacles. Such unethical behaviors generate substantial societal deadweight losses. The overall methodology chosen is unusual for the sector but proved effective and reliable. This approach will be of interest to new researchers investigating issues in complex environments in which the relationship between the practitioner, practitioner experience and knowledge and technical knowledge is an intricately connected one. The methodology belongs to the interpretivist family of academically approved approaches. A thorough review was undertaken of the relevant literature to generate a pilot list of questions. These questions were subject to initial inspection by a group of six industry experts for ease of comprehension. Their feedback was analysed and assimilated, and a revised set of questions was produced. Using the Delphi approach, these questions were presented to 16 industry practitioners to extract their professional insights. Subsequently, two focus study sessions were conducted with six retail investors in Hong Kong and Singapore to optimise the readability of the questioning framework. Part of the questioning framework was then mapped onto a modified version of the Business Model Canvas conceptual framework. Finally, the framework was subject to three layers of validation. Firstly, the framework was used to review four in-sample case studies to ascertain whether all red flags could indeed be uncovered. Secondly, the same processes were repeated with three out-of-sample case studies. Thirdly, three industry practitioners were invited to apply the framework during real life investment analyses to test out whether it was indeed impactful. Validation results at all three layers were affirmative. The concise version of the framework has had a positive reception as a questioning template among retail investors. As for professional investors, the detailed version of the framework has functioned efficiently as their fundamental analysis blueprint. To date, more than 2,000 retail investors and 2,400 professional stakeholders have benefited from the series of spin-off physical and virtual CE (Continuing Education) events associated with this research. The research was informed by and confirmed the key role of corporate governance relating to the ethics of practice as well as environmental, social and governance (ESG) elements

Consequences, Opportunities and Challenges of Modern Biotechnology for Europe - The Analysis Report

Biotechnology is generally considered one of the key technologies of the 21st century, with a potentially wide range of applications in e.g. healthcare, agriculture, and industrial production processes. However, this notion has not yet been substantiated, as the diversity of sectors in which biotechnology is applied makes it difficult to investigate its actual degree of diffusion. Against this background and following a request from the European Parliament, the European Commission initiated the Biotechnology for Europe Study (Bio4EU Study). The study's objectives are to assess the contributions of modern biotechnology to the achievement of major European policy goals, and to increase public awareness and understanding of modern biotechnology.This report presents an analysis of the collected data with a view to assessing the contributions of modern biotechnology to major EU policy goals such as economic growth and job creation (Lisbon Agenda), and environmental sustainability and public health (Sustainable Development Strategy). As such, the report can be considered a background document of the Bio4EU synthesis report, which sets out the main findings of the study.JRC.J.5-Agriculture and Life Sciences in the Econom

Shared Tastes: Economic Development, Local Food, and Kitchen Incubators in New York City

In the past few decades, urban innovations for local food production have begun to gain traction. From rooftop honey production on the Upper West Side to urban farms at Brooklyn Grange, nut milks in Gowanus, and chocolatiers in Bushwick, the presence of small-scale food manufacturing is gaining visibility in the city. However, there is a mismatch in infrastructure for these small producers, as much of the city’s industrial spaces and supply and distribution chains were built to accommodate conventional large scale production. As entrepreneurial food firms attempt to secure a foothold in the city’s manufacturing economy, many are resorting to new cost-sharing measures. The formal sharing of commercial kitchens is one such measure. New York City now has eight private and nonprofit kitchen incubators and two in development. The characteristics of these spaces and the goals of the firms they host vary significantly. Buoyed by a desire to drive economic growth, retain New York City’s manufacturing jobs, and promote locally produced goods, city representatives and stakeholders have extolled the benefits of kitchen incubators. This study explores the characteristics and goals of New York City’s various models of incubator kitchens and how they contribute to (or undermine) economic development and the food economy. Using the lenses of local economic development and food systems planning, it also assesses the economic, health, sustainability, and equity implications of kitchen incubators in New York City. This thesis contributes to existing planning research and theory on the benefits and challenges of supporting early development of firms in a nascent sector in the city’s economy and in creating more “local” food systems in urban environments

ERM Annual Report 2013: Monitoring and Managing Restructuring in the 21st Century

[Excerpt] The 2013 annual report from the European Restructuring Monitor (ERM) presents a retrospective of over a decade of measuring the impact of large-scale restructuring activity in Europe. It summarises restructuring trends based on a restructuring database that includes details of over 16,000 large-scale restructuring events – each generally involving at least 100 job losses or gains. In particular, the report focuses on comparing activity in the pre-crisis period (2003–2008) with the post-crisis period (2008–2013) in order to identify changes in the prevalence of different restructuring practices, and to show which sectors have been disproportionately affected, in employment terms, by the global recession. The report also includes a critical assessment of all ERM activities including the two newer policy-oriented databases: public support instruments and restructuring legislation. Finally, the report places the spotlight on the phenomenon of offshoring, charting the decline in offshoring activity by European firms since the onset of the crisis

From Financial Liberalization to Financial Integration: A Legal Theory of Finance Reinterpretation of the Asian Financial Crisis and the Implications for the Future of Thailand and South East Asia

This dissertation explores the role of law in the financial development of an emerging economic country. Its main proposition is that law plays a fundamental part in both the construction and the subsequent failure of a financial system, in addition to the function of reducing frictions and distortions in order to maintain the orderly running of the market. The dissertation illustrates the aforementioned proposition with an in-depth case study of the Asian Financial Crisis (AFC) which was initially rooted in the Thai financial sector. Aided by the analytical paradigm offered by Legal Theory of Finance, it parses the legal and institutional aspects of the rapidly developing financial markets in Thailand and her investing partners. This allows the ensuing Crisis to be seen from the previously underexplored institutional underpinning of the volatile financial cycle which characterized the region at the time. Subsequently, the dissertation employs the same intellectual framework in order to explain the post-crisis reform initiatives and their systemic implications for the regional financial architecture under the auspices of the Association of the South East Asian Nations. This dissertation cuts across a number of disciplines: law and finance, law and economic development, financial and banking regulation, international financial law, to name but a few