181 research outputs found
CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications
Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non-
Linear (ELIN) systems. They can handle large-signals in a low power environment under half
the capacitor area required by the more popular ELIN Log-domain filters. Their inherent
class-AB nature stems from the odd property of the sinh function at the heart of their
companding operation. Despite this early realisation, the Sinh filtering paradigm has not
attracted the interest it deserves to date probably due to its mathematical and circuit-level
complexity.
This Thesis presents an overview of the CMOS weak inversion Sinh filtering
paradigm and explains how biomedical systems of low- to audio-frequency range could
benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of
high order Sinh continuous–time filters and more importantly to confirm their micro-power
consumption and 100+ dB of DR through measured results presented for the first time.
Novel high order Sinh topologies are designed by means of a systematic
mathematical framework introduced. They employ a recently proposed CMOS Sinh
integrator comprising only p-type devices in its translinear loops. The performance of the
high order topologies is evaluated both solely and in comparison with their Log domain
counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a
corresponding and also novel Log domain class-AB topology, confirming that Sinh filters
constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense
of higher complexity and power consumption. The theoretical findings are validated by
means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a
0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of
~60dB and 74μW power consumption from 2V power supply
Log-domain Universal Biquad Filter Design Using Lossy Integrators
In this paper, a new current mode low voltage log domain Class A universal biquad filter is proposed. The proposed circuit is derived from the block diagram based on Kerwin-Huelsman-Newcomb (KHN) circuit using lossy integrators. The circuit can provide second-order low pass,band pass and high pass filter characteristics. State space method and translinear principle is used for circuit synthesis.The natural frequency f0 and quality factor Q of the circuit is electronically tunable by varying amplitudes of the current sources. PSpice simulation results are given in order to verify the theoretical analysis. The simulations are performed with both ideal transistor models and AT&T CBIC-R type real transistor models
Log-Domain Current-mode Quadrature Sinusoidal Oscillator
A log-domain current-mode quadrature sinusoidal oscillator based on lossless integrators is presented. The circuit is a direct realization of a first-order differential equation for obtaining the lossy and lossless integrators. Each of the log-domain lossless integrators is realized by using only NPN transistors and a grounded capacitor for achieving low-power and fast response. The proposed oscillator uses two-lossless integrator loop which can be electronically tuned through bias currents. A validated BJT model which is used in SPICE simulation operated from a single power supply as low as 2.5V. The oscillation frequency is controlled over four decades of frequency. The total harmonic distortions for two-phases QSO (12MHz) is obtained around 0.93% which enables fully integrated in telecommunication systems. The proposed circuit is also suitable for high-frequency applications. Nonideality studies are included and PSpice simulation results confirm the theoretical results
Design of log domain differential class AB universal biquad filter by employing lossy integrators
A new current mode low voltage differential Class AB second order universal biquad filter has been designed in this work. In design process, inspiring from Kerwin-Huelsman-Newcomb circuit, the circuit is realized with lossy integrators. The circuit has fundamental filter outputs namely; low pass, high pass and band pass. All pass and notch filter outputs have also been obtained by using additional circuits. In circuit design process, the state space method and translinear principle have been used. Two of the circuit parameters are electronically tunable which are the quality factor Q and the pole frequency f0. PSpice circuit simulations have been obtained to check the theoretical results’ validity. In PSpice simulations, both ideal and AT&T CBIC-R type real transistor models have been used
Ultra-Low-Power Configurable Analog Signal Processor for Wireless Sensors
The demand for on-chip low-power Complementary Metal Oxide Semiconductor (CMOS) analog signal processing has significantly increased in recent years. Digital signal processors continue to shrink in size as transistors half in size every two years. However, digital signal processors (DSP\u27s) notoriously use more power than analog signal processors (APS\u27s). This thesis presents a configurable analog signal processor (CASP) used for wireless sensors. This CASP contains a multitude of processing blocks include the following: low pass filter (LPF), high pass filter (HPF) integrator, differentiator, operational transconductance amplifier (OTA), rectifier with absolute value functionality, and multiplier. Each block uses current-mode processing and operates in the sub-threshold region of operation. Current-mode processing allows for noise reduction, lower power consumption, and better dynamic range. Each block contains configurable current sources and capacitor banks for maximum adaptability. The blocks were designed, simulated, and fabricated in Cadence using IBM\u27s 130nm CMOS process. The processing blocks were combined into a four by three array and connected using specially designed interconnect fabric. A test structure including the LPF, HPF, and multiplier was also constructed for characterization purposes. The main goals for this project are frequency compression and creating a non-linear energy operator for neural spike detection.
The test results for the low-pass filter, integrator, and frequency divider reflected the simulated values. The other blocks didn\u27t perform as well as in simulation. The interconnect fabric ties all the blocks together and achieved maximum configurability with negligible attenuation. In simulation, frequency compression was achieved with 30u[micro]W of power from a 1V supply rail
Front-end receiver for miniaturised ultrasound imaging
Point of care ultrasonography has been the focus of extensive research over the past few decades. Miniaturised, wireless systems have been envisaged for new application areas, such as capsule endoscopy, implantable ultrasound and wearable ultrasound. The hardware constraints of such small-scale systems are severe, and tradeoffs between power consumption, size, data bandwidth and cost must be carefully balanced. To address these challenges, two synthetic aperture receiver architectures are proposed and compared. The architectures target highly miniaturised, low cost, B-mode ultrasound imaging systems. The first architecture utilises quadrature (I/Q) sampling to minimise the signal bandwidth and computational load. Synthetic aperture beamforming is carried out using a single-channel, pipelined protocol in order to minimise system complexity and power consumption. A digital beamformer dynamically apodises and focuses the data by interpolating and applying complex phase rotations to the I/Q samples. The beamformer is implemented on a Spartan-6 FPGA and consumes 296mW for a frame rate of 7Hz. The second architecture employs compressive sensing within the finite rate of innovation (FRI) framework to further reduce the data bandwidth. Signals are sampled below the Nyquist frequency, and then transmitted to a digital back-end processor, which reconstructs I/Q components non-linearly, and then carries out synthetic aperture beamforming. Both architectures were tested in hardware using a single-channel analogue front-end (AFE) that was designed and fabricated in AMS 0.35μm CMOS. The AFE demodulates RF ultrasound signals sequentially into I/Q components, and comprises a low-noise preamplifier, mixer, programmable gain amplifier (PGA) and lowpass filter. A variable gain low noise preamplifier topology is used to enable quasi-exponential time-gain control (TGC). The PGA enables digital selection of three gain values (15dB, 22dB and 25.5dB). The bandwidth of the lowpass filter is also selectable between 1.85MHz, 510kHz and 195kHz to allow for testing of both architectural frameworks. The entire AFE consumes 7.8 mW and occupies an area of 1.5×1.5 mm. In addition to the AFE, this thesis also presents the design of a pseudodifferential, log-domain multiplier-filter or “multer” which demodulates low-RF signals in the current-domain. This circuit targets high impedance transducers such as capacitive micromachined ultrasound transducers (CMUTs) and offers a 20dB improvement in dynamic range over the voltage-mode AFE. The bandwidth is also electronically tunable. The circuit was implemented in 0.35μm BiCMOS and was simulated in Cadence; however, no fabrication results were obtained for this circuit. B-mode images were obtained for both architectures. The quadrature SAB method yields a higher image SNR and 9% lower root mean squared error with respect to the RF-beamformed reference image than the compressive SAB method. Thus, while both architectures achieve a significant reduction in sampling rate, system complexity and area, the quadrature SAB method achieves better image quality. Future work may involve the addition of multiple receiver channels and the development of an integrated system-on-chip.Open Acces
Methods for synthesis of multiple-input translinear element networks
Translinear circuits are circuits in which the exponential relationship between the output current and input voltage of a circuit element is exploited to realize various algebraic or differential equations. This thesis is concerned with a subclass of translinear circuits, in which the basic translinear element, called a multiple-input translinear element (MITE), has an output current that is exponentially related to a weighted sum of its input voltages. MITE networks can be used for the implementation of the same class of functions as traditional translinear circuits. The implementation of algebraic or (algebraic) differential equations using MITEs can be reduced to the implementation of the product-of-power-law (POPL) relationships, in which an output is given by the product of inputs raised to different powers. Hence, the synthesis of POPL relationships, and their optimization with respect to the relevant cost functions, is very important in the theory of MITE networks.
In this thesis, different constraints on the topology of POPL networks that result in desirable system behavior are explored and different methods of synthesis, subject to these constraints, are developed. The constraints are usually conditions on certain matrices of the network, which characterize the weights in the relevant MITEs. Some of these constraints are related to the uniqueness of the operating point of the network and the stability of the network. Conditions that satisfy these constraints are developed in this work. The cost functions to be minimized are the number of MITEs and the number of input gates in each MITE. A complete solution to POPL network synthesis is presented here that minimizes the number of MITEs first and then minimizes the number of input gates to each MITE. A procedure for synthesizing POPL relationships optimally when the number of gates is minimal, i.e., 2, has also been developed here for the single--output case. A MITE structure that produces the maximum number of functions with minimal reconfigurability is developed for use in MITE field--programmable analog arrays. The extension of these constraints to the synthesis of linear filters is also explored, the constraint here being that the filter network should have a unique operating point in the presence of nonidealities. Synthesis examples presented here include nonlinear functions like the arctangent and the gaussian function which find application in analog implementations of particle filters. Synthesis of dynamical systems is presented here using the examples of a Lorenz system and a sinusoidal oscillator. The procedures developed here provide a structured way to automate the synthesis of nonlinear algebraic functions and differential equations using MITEs.Ph.D.Committee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradle
Realization of Integrable Low- Voltage Companding Filters for Portable System Applications
Undoubtedly, today’s integrated electronic systems owe their remarkable performance
primarily to the rapid advancements of digital technology since 1970s. The various
important advantages of digital circuits are: its abstraction from the physical details of
the actual circuit implementation, its comparative insensitiveness to variations in the
manufacturing process, and the operating conditions besides allowing functional
complexity that would not be possible using analog technology. As a result, digital
circuits usually offer a more robust behaviour than their analog counterparts, though
often with area, power and speed drawbacks. Due to these and other benefits, analog
functionality has increasingly been replaced by digital implementations.
In spite of the advantages discussed above, analog components are far from
obsolete and continue to be key components of modern electronic systems. There is
a definite trend toward persistent and ubiquitous use of analog electronic circuits in
day-to-day life. Portable electronic gadgets, wireless communications and the
widespread application of RF tags are just a few examples of contemporary
developments. While all of these electronic systems are based on digital circuitry,
they heavily rely on analog components as interfaces to the real world. In fact, many
modern designs combine powerful digital systems and complementary analog
components on a single chip for cost and reliability reasons. Unfortunately, the design
of such systems-on-chip (SOC) suffers from the vastly different design styles of
analog and digital components. While mature synthesis tools are readily available for
digital designs, there is hardly any such support for analog designers apart from wellestablished
PSPICE-like circuit simulators. Consequently, though the analog part
usually occupies only a small fraction of the entire die area of an SOC, but its design
often constitutes a major bottleneck within the entire development process.
Integrated continuous-time active filters are the class of continuous-time or
analog circuits which are used in various applications like channel selection in radios,
anti-aliasing before sampling, and hearing aids etc. One of the figures of merit of a
filter is the dynamic range; this is the ratio of the largest to the smallest signal that can
be applied at the input of the filter while maintaining certain specified performance.
The dynamic range required in the filter varies with the application and is decided by
the variation in strength of the desired signal as well as that of unwanted signals that are to be rejected by the filter. It is well known that the power dissipation and the
capacitor area of an integrated active filter increases in proportion to its dynamic
range. This situation is incompatible with the needs of integrated systems, especially
battery operated ones. In addition to this fundamental dependence of power dissipation
on dynamic range, the design of integrated active filters is further complicated by the
reduction of supply voltage of integrated circuits imposed by the scaling down of
technologies to attain twin objective of higher speed and lower power consumption in
digital circuits. The reduction in power consumption with decreasing supply voltage
does not apply to analog circuits. In fact, considerable innovation is required with a
reduced supply voltage even to avoid increasing power consumption for a given signal
to noise ratio (S/N). These aspects pose a great hurdle to the active filter designer.
A technique which has attracted the attention of circuit designers as a possible
route to filters with higher dynamic range per unit power consumption is
“companding”. Companding (compression-expansion) filters are a very promising
subclass of continuous-time analog filters, where the input (linear) signal is initially
compressed before it will be handled by the core (non-linear) system. In order to
preserve the linear operation of the whole system, the non-linear signal produced by
the core system is converted back to a linear output signal by employing an
appropriate output stage. The required compression and expansion operations are
performed by employing bipolar transistors in active region or MOS transistors in
weak inversion; the systems thus derived are known as logarithmic-domain (logdomain)
systems. In case MOS transistors operated in saturation region are employed,
the derived structures are known as Square-root domain systems. Finally, the third
class of companding filters can also be obtained by employing bipolar transistors in
active region or MOS transistors in weak inversion; the derived systems are known as
Sinh-domain systems. During the last several years, a significant research effort has been already
carried out in the area of companding circuits. This is due to the fact that their main
advantages are the capability for operation in low-voltage environment and large
dynamic range originated from their companding nature, electronic tunability of the
frequency characteristics, absence of resistors and the potential for operations in varied
frequency regions.Thus, it is obvious that companding filters can be employed for implementing
high-performance analog signal processing in diverse frequency ranges. For example,
companding filters could be used for realizing subsystems in: xDSL modems, disk
drive read channels, biomedical electronics, Bluetooth/ZigBee applications, phaselocked
loops, FM stereo demodulator, touch-tone telephone tone decoder and
crossover network used in a three-way high-fidelity loudspeaker etc.
A number of design methods for companding filters and their building blocks
have been introduced in the literature. Most of the proposed filter structures operate
either above 1.5V or under symmetrical (1.5V) power supplies. According to data that
provides information about the near future of semiconductor technology, International
Technology Roadmap for Semiconductors (ITRS), in 2013, the supply voltage of digital
circuits in 32 nm technology will be 0.5 V. Therefore, the trend for the implementation of
analog integrated circuits is the usage of low-voltage building blocks that use a single
0.5-1.5V power supply.
Therefore, the present investigation was primarily concerned with the study and
design of low voltage and low power Companding filters. The work includes the
study about: the building blocks required in implementing low voltage and low power
Companding filters; the techniques used to realize low voltage and low power
Companding filters and their various areas of application.
Various novel low voltage and low power Companding filter designs have been
developed and studied for their characteristics to be applied in a particular portable
area of application. The developed designs include the N-th order universal
Companding filter designs, which have been reported first time in the open literature.
Further, an endeavor has been made to design Companding filters with orthogonal
tuning of performance parameters so that the designs can be simultaneously used for
various features. The salient features of each of the developed circuit are described.
Electronic tunability is one of the major features of all of the designs. Use of
grounded capacitors and resistorless designs in all the cases makes the designs suitable
for IC technology. All the designs operate in a low-voltage and low-power
environment essential for portable system applications.
Unless specified otherwise, all the investigations on these designs are based on the
PSPICE simulations using model parameters of the NR100N bipolar transistors and BSIM 0.35μm/TSMC 0.25μm /TSMC 0.18μm CMOS process MOS transistors. The
performance of each circuit has been validated by comparing the characteristics
obtained using simulation with the results present in the open literature.
The proposed designs could not be realized in silicon due to non-availability of
foundry facility at the place of study. An effort has already been started to realize
some of the designs in silicon and check their applicability in practical circuits. At the
basic level, one of the proposed Companding filter designs was implemented using the
commercially available transistor array ICs (LM3046N) and was found to verify the
theoretical predictions obtained from the simulation results
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