234 research outputs found

    An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

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    In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper

    Delamination-and electromigration-related failures in solar panels—a review

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    The reliability of photovoltaic (PV) modules operating under various weather conditions attracts the manufacturer’s concern since several studies reveal a degradation rate higher than 0.8% per year for the silicon-based technology and reached up to 2.76% per year in a harsh climate. The lifetime of the PV modules is decreased because of numerous degradation modes. Electromigration and delamination are two failure modes that play a significant role in PV modules’ output power losses. The correlations of these two phenomena are not sufficiently explained and understood like other failures such as corrosion and potential-induced degradation. Therefore, in this review, we attempt to elaborate on the correlation and the influence of delamination and electromigration on PV module components such as metallization and organic materials to ensure the reliability of the PV modules. Moreover, the effects, causes, and the sites that tend to face these failures, particularly the silicon solar cells, are explained in detail. Elsewhere, the factors of aging vary as the temperature and humidity change from one country to another. Hence, accelerated tests and the standards used to perform the aging test for PV modules have been covered in this review

    Reliable Design of Three-Dimensional Integrated Circuits

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    End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

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    End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

    Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

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    Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

    Study of Tantalum nitride diffusion barrier films for coppper interconnect technology

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    As technology progressed to ultra - large scale integration leading to smaller and smaller devices, there are continuous challenges in the fields of materials, processes and circuit designs. Copper is the interconnect material of choice because of its low electrical resistivity and high electromigration resistance. However, copper is quite mobile in silicon at elevated temperatures. Therefore, to prevent the diffusion of copper into silicon, a diffusion barrier layer that has fewer grain boundaries, good adhesion to Si and Si02, high thermal and electrical stability with respect to Cu is necessary. Tantalum nitride compounds have been investigated as potential barrier materials. TaN has a very high melting point of 2950C. It is thermodynamically stable with respect to Cu and has good adhesion to the substrate. It has a dense microstructure and shows good resistance to heavy mobility of Cu in Si and has electrical stability at temperatures upto 750 C. The diffusion barrier properties of Ta and its nitrides for copper metallization at RIT have been investigated. The TaNx films were reactively sputter deposited on Si02 substrates at various N2/AJ- ratios. The influence of nitrogen partial pressure on the electrical and structural properties of the films is studied. It has been observed that as deposited pure Ta is tetragonal, which becomes bcc-Ta with small increase in N2 flow to 5% of the sputtering gas mixture. When the nitrogen flow is increased from 12 up to 20%, amorphous and a mixture of amorphous and crystalline Ta2N phase is formed. The amorphous phase crystallizes when annealed to higher temperatures. An fee- TaN phase is formed at N2 flow of 30%. At higher concentrations of N2; nitrogen rich compounds like Ta5N6, Ta3N5 are formed. During backend semiconductor processing, both Cu and TaN films are subjected to various annealing treatments in N2, 02, and Ar at relatively high temperatures. Since these treatments influence the stability of the metallization it was important to establish the effect of the ambients on the integrity of the copper interconnect. The Cu/TaN/Si02 films were annealed to various temperatures up to 600 C in N2, Ar ambients for 20 min and the thermal stability and barrier effectiveness of the films was studied. Annealing the films to temperatures above 500 C cause de-lamination of films at the Cu/TaN interface, which is attributed to the formation of copper oxides with a high density of voids. This was observed by XRD analyis and SEM. RBS spectra showed diffusion of tantalum into the surface of copper at temperatures ~ 500 to 600 C. Therefore we can conclude that cubic TaN films act as stable barrier films up to 500 C in an inert ambient
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