Cryogenic Characterization of 180 nm CMOS Technology at 100 mK

Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK, extracting I/V characteristics, threshold voltages, and transconductance values, as well as observing their temperature dependence. We find that CMOS devices remain fully operational down to these temperatures, although we observe hysteresis effects in some devices. The measurements described in this paper can be used to inform the future design of CMOS devices intended to be operated in this deep cryogenic regime

Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells

The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors. The use of new production processes introduces a set of parasitic effects that gain more and more importance with the scaling down of the technology. In particular, even small variations of parasitic capacitances in CMOS devices are expected to become an additional source of faulty behaviors in future technologies. This paper analyzes and compares the effect of parasitic capacitance variations in a SRAM memory circuit realized with 65 nm and 32 nm predictive technology model

Designing analog circuits in CMOS

The evolution in CMOS technology dictated by Moore's Law is clearly beneficial for designers of digital circuits, but it presents difficult challenges, such as lowered nominal supply voltages, for their peers in the analog world who want to keep pace with this rapid progression. This article discusses a number of significant items for analog designs in modern and future CMOS processes and possible ways to maintain performance

CMOS current-mode chaotic neurons

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. They have been fabricated in a double-metal, single-poly 1.6 /spl mu/m CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploration of the exponential-law operation of CMOS-BJT's. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation

Characterisation of AMS H35 HV-CMOS monolithic active pixel sensor prototypes for HEP applications

Monolithic active pixel sensors produced in High Voltage CMOS (HV-CMOS) technology are being considered for High Energy Physics applications due to the ease of production and the reduced costs. Such technology is especially appealing when large areas to be covered and material budget are concerned. This is the case of the outermost pixel layers of the future ATLAS tracking detector for the HL-LHC. For experiments at hadron colliders, radiation hardness is a key requirement which is not fulfilled by standard CMOS sensor designs that collect charge by diffusion. This issue has been addressed by depleted active pixel sensors in which electronics are embedded into a large deep implantation ensuring uniform charge collection by drift. Very first small prototypes of hybrid depleted active pixel sensors have already shown a radiation hardness compatible with the ATLAS requirements. Nevertheless, to compete with the present hybrid solutions a further reduction in costs achievable by a fully monolithic design is desirable. The H35DEMO is a large electrode full reticle demonstrator chip produced in AMS 350 nm HV-CMOS technology by the collaboration of Karlsruher Institut f\"ur Technologie (KIT), Institut de F\'isica d'Altes Energies (IFAE), University of Liverpool and University of Geneva. It includes two large monolithic pixel matrices which can be operated standalone. One of these two matrices has been characterised at beam test before and after irradiation with protons and neutrons. Results demonstrated the feasibility of producing radiation hard large area fully monolithic pixel sensors in HV-CMOS technology. H35DEMO chips with a substrate resistivity of 200$\Omega$ cm irradiated with neutrons showed a radiation hardness up to a fluence of $10^{15}$n$_{eq}$cm$^{-2}$ with a hit efficiency of about 99% and a noise occupancy lower than $10^{-6}$ hits in a LHC bunch crossing of 25ns at 150V

Ultra-Stretchable Interconnects for High-Density Stretchable Electronics

The exciting field of stretchable electronics (SE) promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS)-type) process recipes using bulk integrated circuit (IC) microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R) post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic) stretch beyond 3000%, with 10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices.Comment: 13 pages, 5 figure, journal publicatio

PIXEL 2010 - a Resume

The Pixel 2010 conference focused on semiconductor pixel detectors for particle tracking/vertexing as well as for imaging, in particular for synchrotron light sources and XFELs. The big LHC hybrid pixel detectors have impressively started showing their capabilities. X-ray imaging detectors, also using the hybrid pixel technology, have greatly advanced the experimental possibilities for diiffraction experiments. Monolithic or semi-monolithic devices like CMOS active pixels and DEPFET pixels have now reached a state such that complete vertex detectors for RHIC and superKEKB are being built with these technologies. Finally, new advances towards fully monolithic active pixel detectors, featuring full CMOS electronics merged with efficient signal charge collection, exploiting standard CMOS technologies, SOI and/or 3D integration, show the path for the future. This r\'esum\'e attempts to extract the main statements of the results and developments presented at this conference.Comment: 8 pages, 19 figures, conference summar

Segmented optical transmitter comprising a CMOS driver array and an InP IQ-MZM for advanced modulation formats

Segmented Mach-Zehnder modulators are promising solutions to generate complex modulation schemes in the migration towards optical links with a higher-spectral efficiency. We present an optical transmitter comprising a segmented-electrode InP IQ-MZM, capable of multilevel optical signal generation (5-bit per I/Q arm) by employing direct digital drive from integrated, low-power (1W) CMOS binary drivers. We discuss the advantages and design tradeoffs of the segmented driver structure and the implementation in a 40 nm CMOS technology. Multilevel operation with combined phase and amplitude modulation is demonstrated experimentally on a single MZM of the device for 2-ASK-2PSK and 4-ASK-2-PSK, showing potential for respectively 16-QAM and 64-QAM modulation in future assemblies