41 research outputs found

    Fabrication and characterisation of copper diffusion barrier layers for future interconnect applications

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    The focus of this thesis is the fabrication and characterisation of ultra-thin self-forming Cu diffusion barrier layers for future interconnect technologies. These barrier layers form by the chemical interaction of an expelled metal from a copper alloy with the surface of a dielectric material to form a stable chemical species suitable for integration into future interconnect fabrication strategies. Studies of both manganese and aluminium as the alloying elements were undertaken and the characterisation techniques included x-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM) and X-ray absorption spectroscopy (XAS) and secondary ion mass spectroscopy (SIMS). Electrical characterisation measurements used to establish the effectiveness of the barrier layers at preventing copper diffusion were performed on fabricated metal-oxide-semiconductor (MOS) structures. A novel approach involving interface chemistry studies and MOS device fabrication on the same dielectric substrate was successfully demonstrated. Barrier formation on a range of prototype low-k dielectric materials with different carbon concentrations and porosities were undertaken and surface chemical modifications prior to barrier layer formation were also investigated. The results show that both Mn and Al are effective at preventing copper diffusion into SiO2, but the inherent porous structure of low-k dielectrics present significant challenges to barrier layer formation, particularly at the dimensional range required for future technology nodes

    Contact Resistance Evolution and Degradation of Highly Cycled Micro-Contacts

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    Reliable microelectromechanical systems (MEMS) switches are critical for developing high performance radio frequency circuits like phase shifters. Engineers have attempted to improve reliability and lifecycle performance using novel contact metals, unique mechanical designs and packaging. Various test fixtures including: MEMS devices, atomic force microscopes (AFM) and nanoindentors have been used to collect resistance and contact force data. AFM and nanoindentor test fixtures allow direct contact force measurements but are severely limited by low resonance sensors, and therefore low data collection rates. This thesis reports the contact resistance evolution results and fabrication of thin film micro-contacts dynamically tested up to 3kHz. The contacts consisted of a lower contact of evaporated Au and a thin film upper contact, consisting of sputtered Au, Ru or RuO2, with an Au electroplated structural layer. The fixed-fixed beam was designed with sufficient restoring force to overcome adhesion. The hemisphere-upper and planar-lower contacts are mated with a calibrated, external load resulting in approximately 200muN of contact force and are cycled in excess of 10 to the 7th power times or until failure. In addition, Au-Au contact pairs with a hemispherical upper an engineered lower contact were tested. These lower engineered contacts were constructed using gray-scale lithography. Contact resistance was measured, in situ, using Holm\u27s a cross-bar configuration and the entire apparatus was isolated from external vibration and housed in an enclosure to minimize contamination due to the ambient environment. Additionally, contact cycling and data collection are automated using a computer, integrated lab equipment and LabVIEW. Results include contact resistance measurements of Au, Ru and RuO2 samples and lifetime testing up to 323.6 million cycles

    Copper Diffusion Barrier Deposition on Integrated Circuit Devices by Atomic Layer Deposition Technique

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    Transfer from aluminum to copper metallization and decreasing feature size of integrated circuit devices generated a need for new diffusion barrier process. Copper metallization comprised entirely new process flow with new materials such as low-k insulators and etch stoppers, which made the diffusion barrier integration demanding. Atomic Layer Deposition technique was seen as one of the most promising techniques to deposit copper diffusion barrier for future devices. Atomic Layer Deposition technique was utilized to deposit titanium nitride, tungsten nitride, and tungsten nitride carbide diffusion barriers. Titanium nitride was deposited with a conventional process, and also with new in situ reduction process where titanium metal was used as a reducing agent. Tungsten nitride was deposited with a well-known process from tungsten hexafluoride and ammonia, but tungsten nitride carbide as a new material required a new process chemistry. In addition to material properties, the process integration for the copper metallization was studied making compatibility experiments on different surface materials. Based on these studies, titanium nitride and tungsten nitride processes were found to be incompatible with copper metal. However, tungsten nitride carbide film was compatible with copper and exhibited the most promising properties to be integrated for the copper metallization scheme. The process scale-up on 300 mm wafer comprised extensive film uniformity studies, which improved understanding of non-uniformity sources of the ALD growth and the process-specific requirements for the ALD reactor design. Based on these studies, it was discovered that the TiN process from titanium tetrachloride and ammonia required the reactor design of perpendicular flow for successful scale-up. The copper metallization scheme also includes process steps of the copper oxide reduction prior to the barrier deposition and the copper seed deposition prior to the copper metal deposition. Easy and simple copper oxide reduction process was developed, where the substrate was exposed gaseous reducing agent under vacuum and at elevated temperature. Because the reduction was observed efficient enough to reduce thick copper oxide film, the process was considered also as an alternative method to make the copper seed film via copper oxide reduction.Vuoden 2006 lopussa amerikkalainen mikroprosessorien valmistaja Intel aloitti kotitietokoneisiin suunnatun uuden sukupolven mikroprosessorin (CoreTM2 Duo, CoreTM2 quad-core and Xeon) valmistuksen. TÀmÀn mahdollisti uusi prosessimenetelmÀ/materiaali, jota kÀytettiin transistorin pinnalla olevaan eristekalvoon, joka oli ainoastaan kymmenkunta atomikerrosta paksu. KysymyksessÀ oli transistoritekniikan suurin muutos 1960-luvun jÀlkeen, mikÀ mahdollisti entistÀ pienemmÀn ja tehokkaamman mikroprosessorin valmistuksen. Vaikka uutinen vastaanotettiin myös Suomessa useissa tiedotusvÀlineissÀ, vain harva tiesi ettÀ kyseinen atomikerroskasvatusmenetelmÀ, ALD (= Atomic Layer Deposition), ja tuolla menetelmÀllÀ kasvatettu kalvo oli Suomessa kehitetty. TÀmÀ olikin tiettÀvÀsti ensimmÀinen kerta kun Suomessa kehitettyÀ teknologiaa kÀytettiin mikroprosessorien massatuotantoon. VÀitöskirjatyössÀni tutkitaan erÀstÀ toista prosessivaihetta mikroprosessorin valmistuksessa, jossa voitaisiin mahdollisesti kÀyttÀÀ ALD-menetelmÀÀ tulevaisuudessa. Olemme kehittÀneet ALD-menetelmÀllÀ kasvatettavia materiaaleja, jotka soveltuvat diffuusionestokalvoiksi mikroprosessoriin. Diffuusionestokalvoa tarvitaan erottamaan johteet ja eristeet toisistaan mikroprosessorin sisÀisessÀ johdotuksessa. Kalvon tehtÀvÀ on estÀÀ atomien kulkeutuminen kalvon toiselta puolelta toiselle puolelle. TyössÀmme on tutkittu erityisesti prosessien integrointiin liittyviÀ haasteita ja pyritty löytÀmÀÀn niihin ratkaisuja. Onnistuimme kehittÀmÀÀn uudeen ALD-prosessin, jonka avulla valmistimme hyvin sÀhköÀ johtavan materiaalin, wolframinitridikarbidin, joka oli myös erinomainen diffusionestomateriaali ja hyvin integroitavissa muihin mikroprosessorin valmistusvaiheisiin

    Growth and chemical characterisation studies of Mn silicate barrier layers on SiO2 and CDO

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    This thesis investigates the suitability of manganese silicate (MnSiO3) as a possible copper interconnect diffusion barrier layer on both a 5.4 nm thick thermally grown SiO2 and a low dielectric constant carbon doped oxide (CDO), with the focus of understanding the barrier formation process. The self forming nature of this diffusion barrier layer resulting from the chemical interaction of deposited Mn with the insulating substrate has potential application in future generations of copper interconnect technologies as they are significantly thinner than the conventional deposited barrier layers. The principle technique used to study the interface chemistry resulting from the interaction of deposited manganese with the insulating substrates to form a MnSiO3 layer was x-ray photoelectron spectroscopy (XPS). Transmission electron microscopy (TEM) measurements provided information on the structure of the barrier layers which could be correlated with the XPS results. Significant differences in the extent of the interface interaction which resulted in the formation of the MnSiO3 barrier layer were found to depend on whether the deposited Mn was partially oxidised. The studies performed on the 5.4 nm thermally grown SiO2 confirmed that the growth of the MnSiO3 resulted in a corresponding reduction in the SiO2 layer thickness. Interactions between residual metallic Mn and subsequently deposited copper layers were also investigated and showed that in order to reduce the width of the barrier layer, it was preferable that all the deposited Mn was fully incorporated into the silicate. TEM measurements were also used to investigate thicker thermally deposited Mn/Cu heterostructures on SiO2 which were subsequently annealed in order to study the diffusion interactions between copper and manganese. The formation of Mn silicate layers on low dielectric constant carbon doped oxide (CDO) was also investigated and compared with the formation characteristics on the thermally grown SiO2

    Atomic layer deposition of metals: Precursors and film growth

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    The coating of complex three-dimensional structures with ultrathin metal films is of great interest for current technical applications, particularly in microelectronics, as well as for basic research on, for example, photonics or spintronics. While atomic layer deposition (ALD) has become a well-established fabrication method for thin oxide films on such geometries, attempts to develop ALD processes for elemental metal films have met with only mixed success. This can be understood by the lack of suitable precursors for many metals, the difficulty in reducing the metal cations to the metallic state, and the nature of metals as such, in particular their tendency to agglomerate to isolated islands. In this review, we will discuss these three challenges in detail for the example of Cu, for which ALD has been studied extensively due to its importance for microelectronic fabrication processes. Moreover, we give a comprehensive overview over metal ALD, ranging from a short summary of the early research on the ALD of the platinoid metals, which has meanwhile become an established technology, to very recent developments that target the ALD of electropositive metals. Finally, we discuss the most important applications of metal ALD

    Study of Surface Morphology and Microstructure of Electrodeposited Polycrystalline Cu Films

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    The applications of polycrystalline films range from interconnects in the electronics and semiconductor industry to solar cells and as corrosion protection. Despite their significance, factors that determine their microstructure and morphology remain largely unsolved. The surface and microstructure of electrodeposited polycrystalline Cu films were investigated. This involves looking at the later growth stages of Cu films using different surface and bulk characterization techniques. The surface evolution of an electrodeposited Cu film was imaged in real-time using a Highspeed Atomic Force Microscope (HS-AFM). This provides details about how the film structure coarsens with time. The high-resolution video showed accelerated local grain growth and grain overgrowth at different locations of the film. A combination of both of these mechanisms could drive structural coarsening. The microstructure could play a role in inducing faster growth in certain grains. How the local and large-scale roughness varies with film thickness is studied by scaling analysis. As a complement to scaling analysis, variation in the local slope with thickness is calculated using slope analysis. Rapid growth was observed in the regions where the HS-AFM tip was scanning. The removal of oxygen adlayer from the surface by the tip could promote faster growth in these regions. Pulsed electrodeposition produced Cu films with hexagonal structures. They are known to be twinned which is a desirable feature in applications that require superior mechanical and electrical properties. The effect of electrode potential on grain size was studied. Using a watershed segmentation algorithm, the grain area was calculated from the AFM images. The grain area showed an increasing trend with increasing overpotential. Slope analysis on the ’hexagons’ and the complete films electrodeposited at higher potential revealed higher slopes and distinct slope distribution. Cross-sectional Focused Ion Beam (FIB) milling confirmed that horizontal twins are present in the pulse-deposited Cu films. The hexagonal pyramids with twins could be produced by one of the two mechanisms, stress relaxation during the ’OFF’ period of pulsing or driven by screw dislocation. We attribute the origin of the hexagons to spiralling screw dislocations. A template matching algorithm was developed to try and correlate the surface and microstructural data of a Cu film grown on a microelectrode. It involved matching the AFM and Electron Back Scatter Diffraction (EBSD) data on the later FIB milled sample, thus relating surface topography to crystallographic orientation. The crystallographic orientation of the edge of the microelectrode and its centre showed different orientations, switching from (111) to (110). Twinning was investigated at the edge and the centre of the microelectrode revealing the presence of stacking fault twins in both of these regions

    Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

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    Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

    Design for reliability applied to RF-MEMS devices and circuits issued from different TRL environments

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    Ces travaux de thĂšse visent Ă  aborder la fiabilitĂ© des composants RF-MEMS (commutateurs en particulier) pendant la phase de conception en utilisant diffĂ©rents approches de procĂ©dĂ©s de fabrication. Ça veut dire que l'intĂ©rĂȘt est focalisĂ© en comment Ă©liminer ou diminuer pendant la conception les effets des mĂ©canismes de dĂ©faillance plus importants au lieu d'Ă©tudier la physique des mĂ©canismes. La dĂ©tection des diffĂ©rents mĂ©canismes de dĂ©faillance est analysĂ©e en utilisant les performances RF du dispositif et le dĂ©veloppement d'un circuit Ă©quivalent. Cette nouvelle approche permet Ă  l'utilisateur final savoir comment les performances vont Ă©voluer pendant le cycle de vie. La classification des procĂ©dĂ©s de fabrication a Ă©tĂ© faite en utilisant le Technology Readiness Level du procĂ©dĂ© qui Ă©value le niveau de maturitĂ© de la technologie. L'analyse de diffĂ©rentes approches de R&D est dĂ©crite en mettant l'accent sur les diffĂ©rences entre les niveaux dans la classification TRL. Cette thĂšse montre quelle est la stratĂ©gie optimale pour aborder la fiabilitĂ© en dĂ©marrant avec un procĂ©dĂ© trĂšs flexible (LAAS-CNRS comme exemple de baisse TRL), en continuant avec une approche composant (CEA-Leti comme moyenne TRL) et en finissant avec un procĂ©dĂ© standard co-intĂ©grĂ© CMOS-MEMS (IHP comme haute TRL) dont les modifications sont impossibles.This thesis is intended to deal with reliability of RF-MEMS devices (switches, in particular) from a designer point of view using different fabrication process approaches. This means that the focus will be on how to eliminate or alleviate at the design stage the effects of the most relevant failure mechanisms in each case rather than studying the underlying physics of failure. The detection of the different failure mechanisms are investigated using the RF performance of the device and the developed equivalent circuits. This novel approach allows the end-user to infer the evolution of the device performance versus time going one step further in the Design for Reliability in RF-MEMS. The division of the fabrication process has been done using the Technology Readiness Level of the process. It assesses the maturity of the technology prior to incorporating it into a system or subsystem. An analysis of the different R&D approaches will be presented by highlighting the differences between the different levels in the TRL classification. This thesis pretend to show how reliability can be improved regarding the approach of the fabrication process starting from a very flexible one (LAAS-CNRS as example of low-TRL) passing through a component approach (CEA-Leti as example of medium-TRL) and finishing with a standard co-integrated CMOS-MEMS process (IHP example of high TRL)
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