Hardware for Memristive Neuromorphic Systems with Reliable Programming and Online Learning

Alternative computing technologies are highly sought after due to limitations on transistor fabrication improvements. Fabricated memristive technology allows for a non-volatile analog memory for neuromorphic computing. In an integrated CMOS process, the synapse circuits designed for a spiking neuromorphic system can use memristors to regulate accumulation in the neuron circuits. Testing the fabricated memristive devices composed of hafnium oxide and developing a model to represent the key device characteristics lead to specific design choices in implementing the analog memory core of the synapse circuit. The circuits I designed for neuromorphic computing in this process take advantage of the unique capabilities of the memristive device to store a programmable analog memory reliably and efficiently. I designed the peripheral circuitry required including the circuits for programming the memristor and for online learning capabilities

Hybrid Memristor-CMOS Computer for Artificial Intelligence: from Devices to Systems

Neuromorphic computing systems, which aim to mimic the function and structure of the human brain, is a promising approach to overcome the limitations of conventional computing systems such as the von-Neumann bottleneck. Recently, memristors and memristor crossbars have been extensively studied for neuromorphic system implementations due to the ability of memristor devices to emulate biological synapses, thus providing benefits such as co-located memory/logic operations and massive parallelism. A memristor is a two-terminal device whose resistance is modulated by the history of external stimulation. The principle of the resistance modulation, or resistance switching, for a typical oxide-based memristor, is based on oxygen vacancy migration in the oxide layer through ion drift and diffusion. When applied in computing systems, the memristor is often formed in a crossbar structure and used to perform vector-matrix multiplication operations. Since the values in the matrix can be stored as the device conductance values of the crossbar array, when an input vector is applied as voltage pulses with different pulse amplitudes or different pulse widths to the rows of the crossbar, the currents or charges collected at the columns of the crossbar correspond to the resulting VMM outputs, following Ohm’s law and Kirchhoff’s current law. This approach makes it possible to use physics to execute direct computing of this data-intensive task, both in-memory and in parallel in a single step. First of all, I will present a comprehensive physical model of the TaOx-based memristor device where the internal parameters including electric field, temperature, and VO concentration are self-consistently solved to accurately describe the device operation. Starting from the initial Forming process, the model quantitatively captures the dynamic RS behavior, and can reliably reproduce Set/Reset cycling in a self-consistent manner. Beyond clarifying the nature of the Forming and Set/Reset processes, a bulk-like doping effect was revealed by the model during Set and supported by experimental results. This phenomenon can lead to linear analog conductance modulation with a large dynamic range, which is very beneficial for low-power neuromorphic computing applications. Second, an integrated memristor/CMOS system consisting of a 54×108 passive memristor crossbar array directly fabricated on a CMOS chip is presented. The system includes all necessary analog/digital circuitry (including analog-digital converters and digital-analog converters), digital buses, and a programmable processor to control the digital and analog components to form a complete hardware system for neuromorphic computing applications. With the fully-integrated and reprogrammable chip, we experimentally demonstrated three popular models – a perceptron network, a sparse coding network, and a bilayer principal component analysis system with an unsupervised feature extraction layer and a supervised classification layer – all on the same chip. Beyond VMM operations, the internal dynamics of memristors allow the system to natively process temporal features in the input data. Specifically, a WOx-based memristor with short-term memory effect caused by spontaneous oxygen vacancy diffusion was utilized to implement a reservoir computing system to process temporal information. The spatial information of a digit image can be converted into streaming inputs fed into the memristor reservoir, leading to 100% accuracy for simple 4×5 digit recognition and 88.1% accuracy for the MNIST data set. The system was also employed for solving other nonlinear tasks such as emulating a second-order nonlinear system.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/155040/1/seulee_1.pd

Crossbar-based memristive logic-in-memory architecture

The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.Peer ReviewedPostprint (author's final draft

Optimizations for a Current-Controlled Memristor-based Neuromorphic Synapse Design

The synapse is a key element of neuromorphic computing in terms of efficiency and accuracy. In this paper, an optimized current-controlled memristive synapse circuit is proposed. Our proposed synapse demonstrates reliability in the face of process variation and the inherent stochastic behavior of memristors. Up to an 82% energy optimization can be seen during the SET operation over prior work. In addition, the READ process shows up to 54% energy savings. Our current-controlled approach also provides more reliable programming over traditional programming methods. This design is demonstrated with a 4-bit memory precision configuration. Using a spiking neural network (SNN), a neuromorphic application analysis was performed with this precision configuration. Our optimized design showed up to 82% improvement in control applications and a 2.7x improvement in classification applications compared with other design cases

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM.Postprint (published version

Tailored electrical characteristics in multilayer metal-oxide-based-memristive devices

Auf Mehrlagen-Metalloxiden basierende memristive Bauelemente sind einer der vielversprechendsten Kandidaten für neuromorphes Computing. Allerdings stellen spezifische Anwendungen des neuromorphen Computings unterschiedliche Anforderungen an die memristiven Bauelemente. Eine ungelöste Herausforderung in der technologischen Entwicklung ist daher das maßgeschneiderte Design von memristiven Bauelementen für spezifische Anwendungen. Insbesondere die unterschiedlichen Materialien des Schichtstapels erschweren die Herstellungsprozesse aufgrund einer großen Anzahl von Parametern, wie z. B. der Stapelsequenzen und -dicken und der Qualität sowie der Eigenschaften der einzelnen Schichten. Daher sind systematische Untersuchungen der einzelnen Bauelementparameter besonders entscheidend. Darüber hinaus müssen sie mit einem tiefgreifenden Verständnis der zugrundeliegenden physikalischen Prozesse kombiniert werden, um die Lücke zwischen Materialdesign und elektrischen Eigenschaften der resultierenden memristiven Bauelemente zuschließen. Um memristive Bauelemente mit unterschiedlichen resistiven Schalteigenschaften zu erhalten, werden verschiedene Abfolgen und Kombinationen von drei Metalloxidschichten (TiOx, HfOx, und AlOx) hergestellt und untersucht. Zunächst werden einschichtige Oxidbauelemente untersucht, um Kandidaten für mehrschichtige Stapel zu identifizieren. Zweitens werden zweischichtige TiOx/HfOx Oxidbauelemente hergestellt. Anhand von systematischen Experimenten und statistischen Analysen wird gezeigt, dass die Stöchiometrie, die Dicke, und die Fläche des Bauelements die Betriebsspannungen, die Nichtlinearität beim resistiven Schalten und die Variabilität beeinflussen. Drittens werden TiOx/AlOx/HfOx-basierte Bauelemente hergestellt. Durch das Hinzufügen von AlOx in die zweischichtigen Oxidstapel weisen diese dreischichtigen Bauelemente optimale elektrische Eigenschaften für den Einsatz in neuromorpher Hardware auf, wie z. B. elektroformierungsfreies und strombegrenzungsloses Schalten sowie eine lange Lebensdauer. Die entwickelten memristiven Bauelemente werden in Systeme, wie Kreuzpunkt-Strukturen und Ein-Transistor-ein-Memristor-Konfigurationen integriert. Hier wird die Eignung für effizientes neuromorphes Computing bewertet. Außerdem werden Methoden zur stufenlosen analogen Einstellung des Widerstands der Bauelemente demonstriert. Diese Eigenschaft ermöglicht effiziente neuromorphe Rechenschemata. Diese umfassende Studie beleuchtet die Beziehung zwischen den Bauelementparametern und den elektrischen Eigenschaften von mehrschichtigen memristiven Bauelementen auf Metalloxidbasis. Auf dieser Grundlage werden maßgeschneiderte Methoden für spezifische neuromorphe Anwendungen entwickelt.Multilayer metal-oxide-based-memristive devices are one of the most promising candidates for neuromorphic computing. However, specific applications of neuromorphic computing call for different requirements for memristive devices. Therefore, an open challenge in technological development is the tailored design of memristive devices for specific applications. In particular, multilayer stacks complicate fabrication processes due to a large number of device parameters such as staking sequences and thicknesses, quality, and property of each layer. Therefore, systematic investigations of the individual device parameters are particularly decisive. Moreover, they need to be combined with a profound understanding of the underlying physical processes to bridge the gap between material design and electrical characteristics of the resulting memristive devices. To obtain memristive devices with different resistance switching characteristics, various sequences and combinations of three metal oxide layers (TiOx, HfOx, and AlOx) are fabricated and studied. First, single-layer oxide devices are investigated to find desirable multilayer stacks for memristive devices. Second, TiOx/HfOx-based bilayer oxide devices are fabricated. Via systematic experiments and statistical analysis, it is shown that the stoichiometry, thickness, and device area influence operating voltages, non-linearity in resistive switching, and variability. Third, TiOx/AlOx/HfOx-based devices are fabricated. By adding AlOx into the bilayer oxide stacks, these trilayer devices present favorable electrical features for use in neuromorphic hardware, such as electroforming-free and compliance-free switching as well as long retention. The developed memristive devices are integrated into systems such as crossbar structures and one-transistor-one-memristor configurations. Here, suitability for efficient neuromorphic computing is assessed. Also, methods to tune the device resistance gradually in an analog fashion are demonstrated. This feature allows for efficient neuromorphic computation. This comprehensive study highlights the relationship between device parameters and electrical properties of multilayer metal-oxide-based memristive devices. On this basis, tailoring methodologies are established for specific neuromorphic applications