Applications of the genetic algorithm optimisation approach in the design of high efficiency microwave class E power amplifiers

In this thesis Genetic Algorithm Optimisation Methods (GA) is studied and for the first time used to design high efficiency microwave class E power amplifiers (PAs) and associated load patch antennas. The difficulties of designing high efficiency PAs is that power transistors are highly non linear and classical design techniques only work for resistive loads. There are currently no high efficient and accurate procedures for design high efficiency PAs. To achieve simplified and accurate design procedure, GA and new design quadratic equations are introduced and applied. The performance analysis is based on linear switch models and non linear circuitry push-pull methods. The results of the analytical calculations and experimental verification showed that the power added efficiency (PAE) of the PAs mainly depend on the losses of the active device itself and are nearly independent on the losses of its harmonic networks. Hence, it has been proven that the cheap material PCB FR4 can be used to design high efficiency class E PAs and it also shown that low Q factor networks have only a minor effect on efficiency, allowing a wide bandwidth to be obtained. In additional, a new procedure for designing class E PAs is introduced and applied. The active device (ATF 34143) is used. Good agreement was obtained between predicted analyses and the simulation results (from Microwave Office (AWR) and Agilent ADS software). For the practical realization, class E PAs were fabricated and tested using PCB FR4. The practical results validate computer simulations and the PAE of the class E PAs are more than 71% and Gain is over 3.8 dB when input power (Pin) is equal to 14 dBm at 2 GHz

Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS

Next generation wireless communication technology requires mobile devices and base stations to support multiband multimode frequencies with higher data rate because of the type of enriched and enhanced features and services that are provided to the end user. The challenge for next generation PA designers is to provide high efficiency, output power and good linearity across multiple frequency bands, modulation standards and bandwidth. Current industry solution involves parallel PAs dedicated to a single band of operation. As more and more features are added, more and more PAs will be required with increasing cost, area and complexity. As a solution to this problem, one tunable fully integrated class-F power amplifier with reconfigurable output harmonic termination is proposed, designed, fabricated and tested with a commercially available 0.13µm CMOS process technology. By using the coupling between the primary and the secondary winding of an on chip transformer with a variable secondary termination capacitance, the second and third harmonic short and open circuit frequencies are dynamically tuned from 700 MHz to 1200 MHz and achieve high efficiency and output power. To overcome CMOS process low break down voltage, a series voltage combining approach is used for the power device to boost output power, by allowing the power supply to exceed process limits. The fabricated die was packaged and mounted to a printed circuit board for evaluation. Compared to previously publish fully integrated PAs, our design exhibits superior peak power added efficiency, 48.4%, and decent saturated output power and power gain of 24.6 dBm and 16.5 dB respectively with reconfigurability from 700 MHz to 1200 MHz

Distributed active transformer - a new power-combining andimpedance-transformation technique

In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistor

Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-Ω match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-Ω input and output matching has been fabricated using 0.35-μm CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time

Contributing to Second Harmonic Manipulated Continuum Mode Power Amplifiers and On-Chip Flux Concentrators

The current cellular network consumes a staggering 100 TWh of energy every year. In the coming years, millions of devices will be added to the existing network to realize the Internet of Things (IoT), further increasing its power consumption. An RF power amplifier typically consumes a large proportion of the DC power in a wireless transceiver, improving its efficiency has the largest impact on the overall system. Additionally, amplifiers need to demonstrate high linearity and bandwidth to adhere to constraints imposed by wireless standards and to reduce the number of amplifiers required as an amplifier with a broader bandwidth can potentially replace several narrowband amplifiers. A typical approach to improve efficiency is to present an appropriate load at the harmonics generated by the transistor. Recently proposed continuous modes based on harmonic manipulation, such as class B/J continuum, continuous class F (CCF) and continuous class F-1 (CCF-1), have shown the capability of achieving counteracting requirements viz., high efficiency, high linearity, and broad bandwidth (with a fractional bandwidth greater than 30%). In these classes of amplifiers, the second harmonic is manipulated by placing a reactive second harmonic load and the reactive component of the fundamental load is adjusted while keeping a fixed resistive component of the fundamental load. The first contribution of this work is to investigate the reason for amplifiers designed in classes B/J continuum and CCF to achieve high efficiency at back-off and 1dB compression. In this thesis, we demonstrate that the variation of the phase of the current through the non-linear intrinsic capacitances due to the variation of the phase in the continuum of drain voltage waveforms in Class B/J/J* continuum leads to either a reduction or enhancement of intrinsic drain current. Consequently, a subset of voltage waveforms of the class B/J/J* continuum can be used to design amplifiers with higher P1dB, and efficiency at P1dB than in Class B. A simple choice of this subset is demonstrated with a 2.6GHz Class B/J/J* amplifier, achieving a P1dB of 38.1dBm and PAE at P1dB of 54.7%, the highest output power and efficiency at P1dB amongst narrowband linear amplifiers using the CGH40010 reported to date, at a comparable peak PAE of 72%. Secondly, we propose a new formulation for high-efficiency modes of power amplifiers in which both the in-phase and out-of-phase components of the second harmonic of the current are varied, in addition to the second harmonic component of the voltage. A reduction of the in-phase component of the second harmonic of current allows reduction of the phase difference between the voltage and current waveforms, thereby increasing the power factor and efficiency. Our proposed waveforms offer a continuous design space between class B/J continuum and continuous F-1 achieving an efficiency of up to 91% in theory, but over a wider set of load impedances than continuous class F-1. These waveforms require a short at third and higher harmonic impedances, which are easier to achieve at a higher frequency. The load impedances at the second harmonic are reactive and can be of any value between -j∞ and j∞, easing the amplifier design. A trade-off between linearity and efficiency exists in the newly proposed broadband design space, but we demonstrate inherent broadband capability. The fabricated narrowband amplifier using a GaN HEMT CGH40010F demonstrates 75.9% PAE and 42.2 dBm output power at 2.6 GHz, demonstrating a comparable frequency weighted efficiency for this device to that reported in the literature. IoT devices may be deployed in critical applications such as radar or 5G transceivers of an autonomous vehicle and hence need to operate free of failure. Monitoring the drain current of the RF GaN MMIC would allow to optimize the device performance and protect it from surges in its supply current. Galvanic current sensors rely on the magnetic field generated by the current as a non-invasive method of current sensing. In this thesis, our third major contribution is a planar on-chip magnetic flux concentrator, is enhance the magnetic field at the current sensor, thereby improving the current detection capability of a current sensor. Our layout utilizes a discontinuity in a magnetic via, resulting in penetration of the magnetic field into the substrate. The proposed concentrator has a magnetic gain x1.8 in comparison to air. The permeability of the magnetic core required is 500, much lower than that reported in off-chip concentrators, resulting in a significant easing of the specifications of the material properties of the core. Additionally, we explore a novel three-dimensional spiral-shaped magnetic flux concentrator. It is predicted via simulations that this geometry becomes a necessity to enhance the magnetic field for increased form factor as the magnetic field from a single planar concentrator deteriorates as its size increases

AlGaN/GaN-HEMT power amplifiers with optimized power-added efficiency for X-band applications

This work has arisen out of the strong demand for a superior power-added efficiency (PAE) of AlGaN/GaN high electron mobility transistor (HEMT) high-power amplifiers (HPAs) that are part of any advanced wireless multifunctional RF-system with limited prime energy. Different concepts and approaches on device and design level for PAE improvements are analyzed, e.g. structural and layout changes of the GaN transistor and advanced circuit design techniques for PAE improvements of GaN HEMT HPAs

Transmissor RF de elevado rendimento com duas entradas digitais para sistemas 5G

In recent years, there has been a need to increase the capacity and speed of information transmission, so the communication signals used in mobile communications have been improved to meet the expectations. This will be even more significant in future 5G systems, since due to the high expansion of wireless devices, current 4G systems are starting to push their limits, where only small improvements can be achieved. Which complicates the design of transmitters, since these new signals have a wider bandwidth and a large variation between their average and peak value, causing amplifiers to operate most of the time in a zone where they are not as efficient. For this reason, amplifier architectures not only aim to have high efficiency when operating at maximum signal excursion, but also to increase efficiency in the zone where they will operate most of the time. For this purpose, there are architectures based on supply voltage modulation and load modulation to improve the efficiency at lower powers. This work addresses load modulation architectures, where Doherty and Chireix are the most prominent. In addition, with the increase in digital signal processing capabilities, new amplification architectures based on the load modulation technique have recently been proposed, but instead of using only one RF input, they use two independent digitally controlled inputs. This dissertation aims at implementing a Doherty-Chireix amplifier with two digital inputs to achieve efficient amplification for the 1.7 to 2.4GHz frequency band. In the end it was possible to design and implement a Doherty-Chireix power amplifier, with 700MHz bandwidth, with a gain between 13.9-11.3dB, a maximum power of 45dBm, a PAE of over 60% and peak-to-average power ratio between 5.2-4.1dB.Nos últimos anos, tem havido uma necessidade de aumentar a capacidade e velocidade de transmissão de informação, deste modo os sinais de comunicação utilizados nas comunicações móveis têm evoluído por forma a corresponder as expectativas. Tal será ainda mais significativo nos futuros sistemas 5G, já que devido à elevada expansão de dispositivos sem fio, os atuais sistemas 4G estão a começar a atingir os seus limites, onde apenas pequenas melhorias podem ser alcançadas. Isto vem complicar o projeto dos transmissores, uma vez que estes novos sinais apresentam uma maior largura de banda e uma grande variação entre o seu valor médio e de pico, fazendo com que os amplificadores operem na maior parte do tempo numa zona em que não são tão eficientes. Por esta razão, as arquiteturas de amplificação nos dias de hoje não só visam ter um grande rendimento quando operam com a máxima excursão de sinal, mas também o aumento do rendimento na zona onde irão operar a maior parte do tempo. Nesse sentido existem arquiteturas baseadas em modelação de tensão de alimentação e modelação de carga de modo a melhorar a eficiência a potências mais baixas. Neste trabalho são abordadas arquiteturas de modulação de carga, onde Doherty e Chireix são as que mais se destacam. Para além disso, com o aumento da capacidade de processamento digital de sinal, recentemente foram propostas novas arquiteturas de amplificação que se baseiam nestas técnicas, mas em vez de utilizar apenas uma entrada de RF, usam duas entradas independentes controladas digitalmente. Esta dissertação visa a implementação de um amplificador Doherty-Chireix com duas entras digitais de modo a obter uma amplificação eficiente para uma banda de frequências de 1.7 a 2.4GHz. No final foi possível projetar e implementar um amplificador de potência Doherty-Chireix, com 700MHz de largura de banda, com um ganho compreendido entre 13.9-11.3dB, potência máxima de 45dBm, uma PAE superior a 60% e peak-to-average power ratio entre 5.2-4.1dB.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

2 GHz +14 dBm CMOS power amplifier for Low Power Wide Area Networks

Abstract. The design of a radiofrequency power amplifier (RF PA) for narrowband low-power wide area networks is presented in this thesis. Particularly, this RF PA is compliant with the 3GPP TS 36.101 standard for a NB1 device within the Power Class 6. To minimize silicon area consumption, this CMOS RF PA employs a single-ended single-stage topology, avoiding inter-stage matching network inductors and output baluns. This RF PA produces +14 dBm of output power with a PAE of 25% and an EVM better than 4% (−28 dB). Also, its out-of-band and spurious emissions satisfy the standard specifications with a large margin. Furthermore, it provides high ruggedness, tolerating an antenna mismatch with a VSWR of 8:1

Optimization Of 5.7 Ghz Class E Power Amplifier For The Application Of Envelope Elimination And Restoration

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Rekabetin yoğun olduğu günümüzde tasarımcılar hafif, boyutları daha küçük ve düşük güçle çalışan yüksek performanslı ürün geliştirmenin yollarını aramaktadırlar. RF alıcı uygulamalarında güç kuvvetlendiricileri en fazla güç sarfiyatının olduğu bölümdür. Kablosuz iletişim sistemlerinde güç küvvetlendiricisi verimi maliyeti direkt olarak etkilemektedir. Teorik olarak %100 verim elde edilebilen E-sınıfı güç kuvvetlendiricileri transistorların açık/kapalı durum geçişlerinde güç sarfiyatını minimize edebilmektedir. Ayrıca çıkış gerilimi kaynak gerilimi ile doğrusal değişmektedir. Bu çalışmada E sınıfı güç kuvvetlendiricilerinin tasarım metodları ele alınmıştır. 5.7 GHz de çalışan birinde toplu devre elemanları, diğerinde transmisyon hattı elemanları kullanımış E sınıfı güç kuvvetlendiricileri tasarlanmıştır. Her iki devrede de %50 güç ekli verim (GEV) ve 500mW çıkış gücü elde edilmiştir. Sinyaldeki bozulmayı azaltmak için başvurulan doğrusallaştırma yöntemi Zarf Yoketme ve Tekrar Oluşturma metodudur. E sınıfı kuvvetlendiricinin Zarf Yoketme ve Tekrar Oluşturma yöntemi kullanılarak doğrusallaştırılmasıyla IMD bileşenlerinde 7.5 dB azalmış olup seviyesi gerçek işaretin 20dB altındadır.In today’s competitive, manufactures and product developers are seeking ways to build high performance devices that are lighter in weight, smaller in size and operating at lower power. In transceiver applications one module is responsible for a large portion of the power consumption - the power amplifier. The efficiency of the power amplifier has a direct impact on the cost of the wireless communication system. The class-E amplifier has a maximum theoretical efficiency of 100%. Class E power amplifiers have the ability to minimize power loss during on/off transitions of the transistor. Also, the output voltage varies linearly with the supply voltage. This thesis describes the design and the linearization methodology of the Class E amplifiers. Two class-E amplifiers operating at 5.7 GHz are presented. One of them is a lumped elements based circuit and the other is a transmission lines based circuit. Both circuit show good performance with 50% PAE and have 500mW output power. Envelope elimination and restoration is the linearization method chosen to achieve reduction of signal distortion. Linearization Class E PA using EER system provides an additional 7.5 dB reduction in intermodulation distortion products, achieving a minimum distortion level of 20 dB below the fundamental signals.Yüksek LisansM.Sc