Investigation of graphene as electrode in n-type OFETs and its use in nanometric devices

This work aims to investigate the use of CVD-graphene as electrode material in nanometric channel n-type Organic Field Effect Transistors (OFETs) based on thermally evaporated thin films of the perylene-3,4,9,10-tetracarboxylic acid diimide derivatives (PDIF-CN2 and PDI8-CN2). We firstly explored the electrical response of nano devices with standard bottom-contact/ distributed bottom gate architecture. By a thorough comparison with short channel transistors made with gold electrodes, output characteristics of the graphene-based devices suggests that SCLC contribution is suppressed. Moreover, current on/off ratios independent of the channel length (L) and enhanced response for high longitudinal biases are demonstrated for (L) down to 140 nm. Further advances have been reached by the use of a proper device architecture for nano devices with patterned local gate tracks and an ultra-thin films (8nm) of Hafnium Dioxide as high-k gate dielectric. The largely improved gate modulation results in a proper output currents saturation for channel length down to 200nm, with supply biases of few volts. Through impedance spectroscopy, overlap capacitances and the overall AC response of CVD-graphene electrodes have been investigated as well. The cut-off frequency of the nanodevice has been indirectly evaluated considering the DC transconductance and the measured overlap capacitance of the graphene electrodes. Values of the order of 150 kHz has been obtained for channel lengths of 200nm. Lastly, the organic/graphene interfaces and their injection and extraction phenomena have been further investigated in micrometric architectures. In particular, the problem of contact resistances have been analyzed via Scanning Kelvin Probe Force Microscopy (SKPFM) and the energetics of the interfaces has been reconstructed by the analysis of UV Photoelectron Spectroscopy (UPS) and X-ray Photoelectron Spectroscopy (XPS)

シリコンカーバイド金属-酸化膜-半導体デバイスにおける界面近傍酸化膜トラップのモデリングと評価

筑波大学 (University of Tsukuba)201

MoS2 Transistors Operating at Gigahertz Frequencies

The presence of a direct band gap and an ultrathin form factor has caused a considerable interest in two-dimensional (2D) semiconductors from the transition metal dichalcogenides (TMD) family with molybdenum disulphide (MoS2) being the most studied representative of this family of materials. While diverse electronic elements, logic circuits and optoelectronic devices have been demonstrated using ultrathin MoS2, very little is known about their performance at high frequencies where commercial devices are expected to function. Here, we report on top-gated MoS2 transistors operating in the gigahertz range of frequencies. Our devices show cutoff frequencies reaching 6 GHz. The presence of a band gap also gives rise to current saturation, allowing power and voltage gain, all in the gigahertz range. This shows that MoS2 could be an interesting material for realizing high-speed amplifiers and logic circuits with device scaling expected to result in further improvement of performance. Our work represents the first step in the realization of high-frequency analog and digital circuits based on two-dimensional semiconductors.Comment: Nano Letters (2014), Supplementary information available at http://dx.doi.org/10.1021/nl502863

Microelectromechanical Systems and Devices

The advances of microelectromechanical systems (MEMS) and devices have been instrumental in the demonstration of new devices and applications, and even in the creation of new fields of research and development: bioMEMS, actuators, microfluidic devices, RF and optical MEMS. Experience indicates a need for MEMS book covering these materials as well as the most important process steps in bulk micro-machining and modeling. We are very pleased to present this book that contains 18 chapters, written by the experts in the field of MEMS. These chapters are groups into four broad sections of BioMEMS Devices, MEMS characterization and micromachining, RF and Optical MEMS, and MEMS based Actuators. The book starts with the emerging field of bioMEMS, including MEMS coil for retinal prostheses, DNA extraction by micro/bio-fluidics devices and acoustic biosensors. MEMS characterization, micromachining, macromodels, RF and Optical MEMS switches are discussed in next sections. The book concludes with the emphasis on MEMS based actuators

High-performance Zinc Oxide Thin-Film Transistors For Large Area Electronics

The increasing demand for high performance electronics that can be fabricated onto large area substrates employing low manufacturing cost techniques in recent years has fuelled the development of novel semiconductor materials such as organics and metal oxides, with tailored physical characteristics that are absent in their traditional inorganic counterparts such as silicon. Metal oxide semiconductors, in particular, are highly attractive for implementation into thin-film transistors because of their high charge carrier mobility, optical transparency, excellent chemical stability, mechanical stress tolerance and processing versatility. This thesis focuses on the development of high performance transistors based on zinc oxide (ZnO) semiconducting films grown by spray pyrolysis (SP), a low cost and highly scalable method that has never been used before for the manufacturing of oxide-based thin-film transistors. The physical properties of as-grown ZnO films have been studied using a range of techniques. Despite the simplicity of SP, as-fabricated transistors exhibit electrical characteristics comparable to those obtained from ZnO devices produced using highly sophisticated deposition processes. In particular, electron mobility up to 25 cm2/Vs has been achieved in transistors based on pristine ZnO films grown at 400 °C onto Si/SiO2 substrates utilising aluminium source-drain (S-D) electrodes. A strong dependence of the saturation mobility on the work function of S-D electrodes and the transistor channel length (L) has been established. Short channel transistors are found to exhibit improved performance as compared to long channel ones. This was attributed to grain boundary effects that tend to dominate charge transport in devices with L < 40 μm. High mobility, low operating voltage (<1.5 V) ZnO transistors have also been developed and characterised. This was achieved through the combination of SP, for the deposition of ZnO, and thermally stable solution-processed self-assembling monolayer gate dielectrics. Detailed study of the temperature dependence of the operating characteristics of ZnO transistors revealed a thermally activated electron transport process that was described by invoking the multiple trapping and release model. Importantly, ZnO transistors fabricated by SP are found to exhibit highly stable operating characteristics with a shelf lifetime of several months. The simple SPbased fabrication paradigm demonstrated in this thesis expands the possibilities for the development of advanced simple as well as multi-component oxide semiconductors far beyond those accessible by traditional deposition methods such as sputtering. Furthermore, it offers unprecedented processing scalability hence making it attractive for the manufacturing of future ubiquitous oxide electronics

Integration of highly crystalline C8-BTBT thin-films into simple logic gates and circuits

Highly crystalline organic thin films possess the charge carrier mobilities needed for high-performance, low-cost flexible electronics. However, only few reports exist that show the integration of these films into short-channel organic circuits. This work describes the integration of highly crystalline layers of the thermally and chemically fragile small molecule C8-BTBT. Thin films of this material are processed by a combination of zone-casting and homoepitaxial vacuum evaporation and display an average charge carrier mobility of 7.5 cm2/V in long channel transistors. The integration of these films into a circuit technology based on a 5 μm channel-length bottom-gate bottom-contact transistor topology results in inverters with gains up to 40 as well as a robust 19-stage ring oscillator. This circuit requires the simultaneous operation of 80 TFTs and displays a stage delay of 40 μs, resulting in an operating frequency of 630 Hz at an operating voltage of 10 V. With the help of circuit modelling, we quantify the relationship between the speed of ring oscillators and the contact resistance of individual transistors. Indeed, the successful integration of highly-crystalline layers with high intrinsic mobility stresses the need for advances in contact engineering

Ultrathin CaTiO3 Capacitors: Physics and Application

Scaling of electronic circuits from micro- to nanometer size determined the incredible development in computer technology in the last decades. In charge storage capacitors that are the largest components in dynamic random access memories (DRAM), dielectrics with higher permittivity (high-k) were needed to replace SiO2. Therefore ZrO2 has been introduced in the capacitor stack to allow sufficient capacitance in decreasing structure sizes. To improve the capacitance density per cell area, approaches with three dimensional structures were developed in device fabrication. To further enable scaling for future generations, significant efforts to replace ZrO2 as high-k dielectric have been undertaken since the 1990s. In calculations, CaTiO3 has been identified as a potential replacement to allow a significant capacitance improvement. This material exhibits a significantly higher permittivity and a sufficient band gap. The scope of this thesis is therefore the preparation and detailed physical and electrical characterization of ultrathin CaTiO3 layers. The complete capacitor stacks including CaTiO3 have been prepared under ultrahigh vacuum to minimize the influence of adsorbents or contaminants at the interfaces. Various electrodes are evaluated regarding temperature stability and chemical reactance to achieve crystalline CaTiO3. An optimal electrode was found to be a stack consisting of Pt on TiN. Physical experiments confirm the excellent band gap of 4.0-4.2 eV for ultrathin CaTiO3 layers. Growth studies to achieve crystalline CaTiO3 indicate a reduction of crystallization temperature from 640°C on SiO2 to 550°C on Pt. This reduction has been investigated in detail in transmission electron microscopy measurements, revealing a local and partial epitaxial growth of (111) CaTiO3 on top of (111) Pt surfaces. This preferential growth is beneficial to the electrical performance with an increased relative permittivity of 55 with the advantage of a low leakage current comparable to that in amorphous CaTiO3 layers. A detailed electrical analysis of capacitors with amorphous and crystalline CaTiO3 reveals a relative permittivity of 30 for amorphous and an excellent value of 105 for fully crystalline CaTiO3. The permittivity exhibits a quadratic dependence with applied electric field. Crystalline CaTiO3 shows a 1-3% drop in capacitance density and permittivity at a bias voltage of 1V, which is significantly lower compared to all results for SrTiO3 capacitors measured elsewhere. A capacitance equivalent thickness (CET) below 1.0 nm with current densities 1×10−8 A/cm2 have been achieved on carbon electrodes. Finally, CETs of about 0.5 nm with leakage currents of 1 × 10−7 A/cm2 on top of Pt/TiN fulfill the 2016 DRAM requirements following the ITRS road map of 2012.Die Verkleinerung von elektronischen Bauelementen hin zu nanometerkleinen Strukturen beschreibt die unglaubliche Entwicklung der Computertechnologie in den letzten Jahrzehnten. In Ladungsspeicherkondensatoren, den größten Komponenten in Arbeitsspeichern, wurden dafür Dielektrika benötigt, die eine deutlich höhere Permittivität als SiO2 besitzen. ZrO2 wurde als geeignetes Dielektrikum eingeführt, um eine ausreichende Kapazität bei kleiner werdenen Strukturen sicherzustellen. Zur weiteren Verbesserung der Kapazitätsdichte pro Zellfläche konnten 3D Strukturen in die Chipherstellung integriert werden. Seit den 1990ern wurden parallel bedeutende Anstrengungen unternommen, um ZrO2 als Dielektrikum durch Materialien mit noch höherer Permittivität zu ersetzen. Nach Berechnungen stellt nun CaTiO3 eine mögliche Alternative dar, die eine weitere Verbesserung der Kapazität ermöglicht. Das Material besitzt eine deutlich höhere Permittivität und eine ausreichend große Bandlücke. Diese Arbeit beschäftigt sich deshalb mit Herstellung und detaillierter physikalischer und elektrischer Charakterisierung von extrem dünnen CaTiO3 Schichten. Zusätzlich wurden diverse Elektroden bezüglich ihrer Temperaturstabilität und der chemischen Stabilität untersucht, um kristallines CaTiO3 zu herhalten. Als eine optimale Elektrode stellte sich Pt auf TiN heraus. Physikalische Experimente an extrem dünnen CaTiO3 Schichten bestätigen die Bandlücke von 4,0-4,2 eV. Wachstumsuntersuchungen an kristallinem CaTiO3 zeigen eine Reduktion der Kristallisationstemperatur von 640°C auf SiO2 zu 550°C auf Pt. Diese Reduktion wurde detailliert mittels Transmissionselektronenmikroskopie untersucht. Es konnte für einige Schichten ein partielles lokales epitaktischesWachstum von (111) CaTiO3 auf (111) Pt gemessen werden. Dieses Vorzugswachstum ist vorteilhaft für die elektrischen Eigenschaften durch eine gesteigerte Permittivität von 55 bei gleichzeitig geringem Leckstrom vergleichbar zu amorphen Schichten. Eine genaue elektrische Analyse von Kondensatoren mit amorphen und kristallinem CaTiO3 ergibt eine Permittivität von 30 für amorphe und bis zu 105 für kristalline CaTiO3 Schichten. Die Permittivität zeigt eine quadratische Abhängigheit von der angelegten Spannung. Kristallines CaTiO3 zeigt einen 1-3% Abfall der Permittivität bei 1V, der wesentlich geringer ausfällt als vergleichbare Werte für SrTiO3. Eine zu SiO2 vergleichbare Schichtdicke (CET) von unter 1,0 nm mit Stromdichten von 1×10−8 A/cm2 wurde auf Kohlenstoffsubstraten erreicht. Mit Werten von 0,5 nm bei Leckstromdichten von 1×10−7 A/cm2 auf Pt/TiN Elektroden erfüllen die CaTiO3 Kondensatoren die Anforderungen der ITRS Strategiepläne für Arbeitsspeicher ab 2016

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future