8,731 research outputs found

    Fiabilité de l’underfill et estimation de la durée de vie d’assemblages microélectroniques

    Get PDF
    Abstract : In order to protect the interconnections in flip-chip packages, an underfill material layer is used to fill the volumes and provide mechanical support between the silicon chip and the substrate. Due to the chip corner geometry and the mismatch of coefficient of thermal expansion (CTE), the underfill suffers from a stress concentration at the chip corners when the temperature is lower than the curing temperature. This stress concentration leads to subsequent mechanical failures in flip-chip packages, such as chip-underfill interfacial delamination and underfill cracking. Local stresses and strains are the most important parameters for understanding the mechanism of underfill failures. As a result, the industry currently relies on the finite element method (FEM) to calculate the stress components, but the FEM may not be accurate enough compared to the actual stresses in underfill. FEM simulations require a careful consideration of important geometrical details and material properties. This thesis proposes a modeling approach that can accurately estimate the underfill delamination areas and crack trajectories, with the following three objectives. The first objective was to develop an experimental technique capable of measuring underfill deformations around the chip corner region. This technique combined confocal microscopy and the digital image correlation (DIC) method to enable tri-dimensional strain measurements at different temperatures, and was named the confocal-DIC technique. This techique was first validated by a theoretical analysis on thermal strains. In a test component similar to a flip-chip package, the strain distribution obtained by the FEM model was in good agreement with the results measured by the confocal-DIC technique, with relative errors less than 20% at chip corners. Then, the second objective was to measure the strain near a crack in underfills. Artificial cracks with lengths of 160 μm and 640 μm were fabricated from the chip corner along the 45° diagonal direction. The confocal-DIC-measured maximum hoop strains and first principal strains were located at the crack front area for both the 160 μm and 640 μm cracks. A crack model was developed using the extended finite element method (XFEM), and the strain distribution in the simulation had the same trend as the experimental results. The distribution of hoop strains were in good agreement with the measured values, when the model element size was smaller than 22 μm to capture the strong strain gradient near the crack tip. The third objective was to propose a modeling approach for underfill delamination and cracking with the effects of manufacturing variables. A deep thermal cycling test was performed on 13 test cells to obtain the reference chip-underfill delamination areas and crack profiles. An artificial neural network (ANN) was trained to relate the effects of manufacturing variables and the number of cycles to first delamination of each cell. The predicted numbers of cycles for all 6 cells in the test dataset were located in the intervals of experimental observations. The growth of delamination was carried out on FEM by evaluating the strain energy amplitude at the interface elements between the chip and underfill. For 5 out of 6 cells in validation, the delamination growth model was consistent with the experimental observations. The cracks in bulk underfill were modelled by XFEM without predefined paths. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5°. This approach met the goal of the thesis of estimating the underfill initial delamination, areas of delamination and crack paths in actual industrial flip-chip assemblies.Afin de protéger les interconnexions dans les assemblages, une couche de matériau d’underfill est utilisée pour remplir le volume et fournir un support mécanique entre la puce de silicium et le substrat. En raison de la géométrie du coin de puce et de l’écart du coefficient de dilatation thermique (CTE), l’underfill souffre d’une concentration de contraintes dans les coins lorsque la température est inférieure à la température de cuisson. Cette concentration de contraintes conduit à des défaillances mécaniques dans les encapsulations de flip-chip, telles que la délamination interfaciale puce-underfill et la fissuration d’underfill. Les contraintes et déformations locales sont les paramètres les plus importants pour comprendre le mécanisme des ruptures de l’underfill. En conséquent, l’industrie utilise actuellement la méthode des éléments finis (EF) pour calculer les composantes de la contrainte, qui ne sont pas assez précises par rapport aux contraintes actuelles dans l’underfill. Ces simulations nécessitent un examen minutieux de détails géométriques importants et des propriétés des matériaux. Cette thèse vise à proposer une approche de modélisation permettant d’estimer avec précision les zones de délamination et les trajectoires des fissures dans l’underfill, avec les trois objectifs suivants. Le premier objectif est de mettre au point une technique expérimentale capable de mesurer la déformation de l’underfill dans la région du coin de puce. Cette technique, combine la microscopie confocale et la méthode de corrélation des images numériques (DIC) pour permettre des mesures tridimensionnelles des déformations à différentes températures, et a été nommée le technique confocale-DIC. Cette technique a d’abord été validée par une analyse théorique en déformation thermique. Dans un échantillon similaire à un flip-chip, la distribution de la déformation obtenues par le modèle EF était en bon accord avec les résultats de la technique confocal-DIC, avec des erreurs relatives inférieures à 20% au coin de puce. Ensuite, le second objectif est de mesurer la déformation autour d’une fissure dans l’underfill. Des fissures artificielles d’une longueuer de 160 μm et 640 μm ont été fabriquées dans l’underfill vers la direction diagonale de 45°. Les déformations circonférentielles maximales et principale maximale étaient situées aux pointes des fissures correspondantes. Un modèle de fissure a été développé en utilisant la méthode des éléments finis étendue (XFEM), et la distribution des contraintes dans la simuation a montré la même tendance que les résultats expérimentaux. La distribution des déformations circonférentielles maximales était en bon accord avec les valeurs mesurées lorsque la taille des éléments était plus petite que 22 μm, assez petit pour capturer le grand gradient de déformation près de la pointe de fissure. Le troisième objectif était d’apporter une approche de modélisation de la délamination et de la fissuration de l’underfill avec les effets des variables de fabrication. Un test de cyclage thermique a d’abord été effectué sur 13 cellules pour obtenir les zones délaminées entre la puce et l’underfill, et les profils de fissures dans l’underfill, comme référence. Un réseau neuronal artificiel (ANN) a été formé pour établir une liaison entre les effets des variables de fabrication et le nombre de cycles à la délamination pour chaque cellule. Les nombres de cycles prédits pour les 6 cellules de l’ensemble de test étaient situés dans les intervalles d’observations expérimentaux. La croissance de la délamination a été réalisée par l’EF en évaluant l’énergie de la déformation au niveau des éléments interfaciaux entre la puce et l’underfill. Pour 5 des 6 cellules de la validation, le modèle de croissance du délaminage était conforme aux observations expérimentales. Les fissures dans l’underfill ont été modélisées par XFEM sans chemins prédéfinis. Les directions des fissures de bord étaient en bon accord avec les observations expérimentales, avec une erreur inférieure à 2,5°. Cette approche a répondu à la problématique qui consiste à estimer l’initiation des délamination, les zones de délamination et les trajectoires de fissures dans l’underfill pour des flip-chips industriels

    Architectural optimisation for microelectronic packaging

    No full text
    International audienceThe aim of this paper is to provide a methodical approach for architectural optimization of power microelectronic devices. Because critical parameters of electronic devices are linked with reliability, architectural optimisation, selection of the geometrical parameters of device and optimization of these parameters by iteration method associated by numerical analysis of reliability have to be achieved. In this way, this paper discusses about a methodical and numerical approach for the optimization of reliability in electronic devices, in particular the influence of geometrical parameters on the device reliability

    DEVELOPMENT OF FATIGUE MODELS FOR COPPER TRACES ON PRINTED WIRING ASSEMBLIES UNDER QUASI-STATIC CYCLIC MECHANICAL BENDING

    Get PDF
    This dissertation investigates the fatigue durability of copper (Cu) traces on printed wiring assemblies (PWAs) under quasi-static cyclic mechanical flexure, using experimental results from a set of three-point bending fatigue tests, finite element (FE) modeling of the stresses generated during the cyclic bending tests, and response surfaces (RS) to facilitate iterative assessment of the model constants. Cyclic three-point bend tests were conducted on land grid array (LGA) components during this investigation. Failure analysis revealed the fatigue failure sites to be in the Cu traces, at the outer edge of the foot-print of the solder joint. A three-dimensional, elastic-plastic FE model simulating the event (based on a global and local modeling strategy) was used to determine the stresses and strains occurring at the failure site during the cyclic loading. Parametric studies were conducted to examine the influence of elastic-plastic constitutive behavior on the stress and strain states at the failure site. Results of the parametric studies were captured in compact meta-models, using polynomial response surfaces. The durability data was collected from the experiment and used in conjunction with these models, to develop a set of compatible constitutive and fatigue model constants that best fit the behavior observed. Since the loading was not fully reversed, a mean stress correction factor was needed. Existing correction methods, such as the modified Morrow model, were found to be deficient for tensile means stresses, due to high mean stresses predicted by classical constitutive models. A new correction model was proposed, based on a "tanh" term, which forced a saturation of the mean stress effect at higher stress levels for tensile means stresses. This saturation effect was also considered for compressive loading, termed the BCS model ("B" for "bounded" effect of the mean stresses), and compared with the standard unbounded model, termed the UCS model. A detailed iterative methodology was developed to iterate the Cu elastic-plastic constitutive model constants as well as the cyclic fatigue model constants needed to satisfy the observed durability behavior. This iterative model was based on the average strain values in cross section of the trace, at the failure site. The resulting fatigue model constants were termed the "averaged fatigue constants (AFCs). To further improve on the fatigue constants, the fatigue damage initiation and propagation behavior were considered separately, using a continuum damage mechanics method termed the successive initiation method. In this phase of the study, the constitutive model constants were those determined from the AFC model. This method uses an incremental damage growth concept rather than a classical fracture propagation concept, since there is distributed damage observed in the experiment. The resulting fatigue constants were termed the incremental fatigue constants (IFCs). Finally, the validity of the modeling approach and the developed AFC and IFC model constants are explored, using results from a published case study of four-point cyclic bend tests of leadless chip resistors (LCRs). The model appears to predict the results reasonably well

    Aeronautical Engineering: A continuing bibliography, supplement 120

    Get PDF
    This bibliography contains abstracts for 297 reports, articles, and other documents introduced into the NASA scientific and technical information system in February 1980

    MODELING THE PHYSICS OF FAILURE FOR ELECTRONIC PACKAGING COMPONENTS SUBJECTED TO THERMAL AND MECHANICAL LOADING

    Get PDF
    This dissertation presents three separate studies that examined electronic components using numerical modeling approaches. The use of modeling techniques provided a deeper understanding of the physical phenomena that contribute to the formation of cracks inside ceramic capacitors, damage inside plated through holes, and to dynamic fracture of MEMS structures. The modeling yielded numerical substantiations for previously proposed theoretical explanations. Multi-Layer Ceramic Capacitors (MLCCs) mounted with stiffer lead-free solder have shown greater tolerance than tin-lead solder for single cycle board bending loads with low strain rates. In contrast, flexible terminations have greater tolerance than stiffer standard terminations under the same conditions. It has been proposed that residual stresses in the capacitor account for this disparity. These stresses have been attributed to the higher solidification temperature of lead free solders coupled with the CTE mismatch between the board and the capacitor ceramic. This research indicated that the higher solidification temperatures affected the residual stresses. Inaccuracies in predicting barrel failures of plated through holes are suspected to arise from neglecting the effects of the reflow process on the copper material. This research used thermo mechanical analysis (TMA) results to model the damage in the copper above the glass transition temperature (Tg) during reflow. Damage estimates from the hysteresis plots were used to improve failure predictions. Modeling was performed to examine the theory that brittle fracture in MEMS structures is not affected by strain rates. Numerical modeling was conducted to predict the probability of dynamic failure caused by shock loads. The models used a quasi-static global gravitational load to predict the probability of brittle fracture. The research presented in this dissertation explored drivers for failure mechanisms in flex cracking of capacitors, barrel failures in plated through holes, and dynamic fracture of MEMS. The studies used numerical modeling to provide new insights into underlying physical phenomena. In each case, theoretical explanations were examined where difficult geometries and complex material properties made it difficult or impossible to obtain direct measurements

    THERMAL CYCLING RELIABILITY OF LEAD-FREE SOLDERS (SAC305 AND SN3.5AG) FOR HIGH TEMPERATURE APPLICATIONS

    Get PDF
    Eutectic tin lead was the most widely used solder interconnect in the electronics industry before the adoption of lead-free legislation. But eutectic tin lead solder has a low melting point (183oC) and was not suited for some high temperature applications, such as oil and gas exploration, automotive, and defense. Hence, for these applications, the electronics industry had to rely on specialized solders. In this study, ball grid arrays (BGAs), quad flat packages (QFPs), and surface mount resistors assembled with SAC305 and Sn3.5Ag solder pastes were subjected to thermal cycling from -40oC to 185oC. Commercially available electroless nickel immersion gold (ENIG) board finish was compared to proprietary Sn-based board finish designed for high temperatures. The data analysis showed that the type of solder paste and board finish used did not have an impact on the reliability of BGAs. The failure site was on the package side of the solder joint. The morphology of intermetallic compounds (IMCs) formed after thermal cycling was analyzed

    Rapid Assessment of BGA Fatigue Life Under Vibration Loading

    Get PDF
    Ball Grid Array (BGA) packages are a relatively new package type and have rapidly become the package style of choice. Much high density, high I/O count semiconductor devices are now only offered in this package style. Designers are naturally concerned about the robustness of BGA packages in a vibration environment when their experience base is with products using more traditional compliant gull or J leaded surface mount packages. Because designers simply do not have the experience, tools are needed to assess the vibration fatigue life of BGA packages during early design stages and not have to wait for product qualification testing, or field returns, to determine if a problem exists. This dissertation emphasizes a rapid assessment methodology to determine fatigue life of BGA components. If time and money were not an issue, clearly one would use a general-purpose finite element program to determine the dynamic response of the printed wiring board in the vibration environment. Once the response of the board was determined, one would determine the location and value of the critical stress in the component of interest. Knowing the critical stress, one would estimate the fatigue life from a damage model. The time required building the FEA model, conducting the analysis, and post-process the results would take at least a few days to weeks. This is too time-consuming, except in the most critical applications. It is not a process that can be used in everyday design and what-if simulations. The rapid assessment approach proposed in this research focuses on a physics of failure type approach to damage analysis and involves global and local modeling to determine the critical stress in the component of interest. A fatigue damage model then estimates the life. Once implemented in software, i.e. the new version of CALCE_PWA, the entire fatigue life assessment is anticipated to be executed by an average engineer in real time and take only minutes to generate accurate results

    Numerical analysis of lead-free solder joints: effects of thermal cycling and electromigration

    Get PDF
    To meet the requirements of miniaturization and multifunction in microelectronics, understanding of their reliability and performance has become an important research subject in order to characterise electronics served under various loadings. Along with the demands of the increasing miniaturization of electronic devices, various properties and the relevant thermo-mechanical-electrical response of the lead-free solder joints to thermal cycling and electro-migration become the critical factors, which affect the service life of microelectronics in different applications. However, due to the size and structure of solder interconnects in microelectronics, traditional methods based on experiments are not applicable in the evaluation of their reliability under complex joint loadings. This thesis presents an investigation, which is based on finite-element method, into the performance of lead-free solder interconnects under thermal fatigue and electro-migration, specifically in the areas as follows: (1) the investigation of thermal-mechanical performance and fatigue-life prediction of flip-chip package under different sizes to achieve a further understanding of IMC layer and size effects of a flip chip package under thermal cycling; (2) the establishment of a numerical method, simulating void-formation/crack-propagation based on the results of finite-element analysis, to allow the prediction of crack evolution and failure time for electro-migration reliability of solder bumps; (3) the establishment of a flow-based algorithm for combination effects of thermal-mechanical and electro-migration that was subsequent implemented in to an FE model to evaluate the reliability assessment of service lives associated with a flip chip package
    • …
    corecore