465 research outputs found

    Techniques for low jitter clock multiplication

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 115-121).Phase realigning clock multipliers, such as Multiplying Delay-Locked Loops (MDLL), offer significantly reduced random jitter compared to typical Phase-Locked Loops (PLL). This is achieved by introducing the reference signal directly into their voltage controlled oscillators (VCO) to realign the phase to the clean reference. However, the typical cost of this benefit is a significant increase in deterministic jitter due to path mismatch in the detector as well as analog nonidealities in the tuning circuits. This thesis proposes a mostly-digital tuning technique that drastically reduces deterministic jitter in phase realigning clock multipliers. The proposed technique eliminates path mismatch by using a single-path digital detection method that leverages a scrambling time-to-digital converter (TDC) and correlated double sampling to infer the tuning error from the difference in cycle periods of the output. By using a digital loop filter that consists of a digital accumulator, the tuning technique avoids the analog nonidealities of typical tuning paths. The scrambling TDC is not a contribution of this thesis. A highly-digital MDLL prototype that uses the proposed tuning technique consists of two custom 0.13 [mu]m ICs, an FPGA board, a discrete digital-to-analog converter (DAC) with effective 8 bits, and a simple RC filter. The measured performance (for a 1.6 GHz output and 50 MHz reference) demonstrated an overall jitter of 0.93 ps rms, and estimated random and deterministic jitter of 0.68 ps rms and 0.76 ps peak-to-peak, respectively. The proposed MDLL architecture is especially suitable for digital ICs, since its highly-digital architecture is mostly compatible with digital design flows, which eases its porting between technologies.by Belal Moheedin Helal.Ph.D

    LOW-POWER FREQUENCY SYNTHESIS BASED ON INJECTION LOCKING

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    Ph.DDOCTOR OF PHILOSOPH

    Index to 1983 NASA Tech Briefs, volume 8, numbers 1-4

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    Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1983 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

    Ultrashort, High Power, And Ultralow Noise Mode-locked Optical Pulse Generation Using Quantum-dot Semiconductor Lasers

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    This dissertation explores various aspects and potential of optical pulse generation based on active, passive, and hybrid mode-locked quantum dot semiconductor lasers with target applications such as optical interconnect and high speed signal processing. Design guidelines are developed for the single mode operation with suppressed reflection from waveguide discontinuities. The device fabrication procedure is explained, followed by characteristics of FP laser, SOA, and monolithic two-section devices. Short pulse generation from an external cavity mode-locked QD two-section diode laser is studied. High quality, sub-picosecond (960 fs), high peak power (1.2 W) pulse trains are obtained. The sign and magnitude of pulse chirp were measured for the first time. The role of the self-phase modulation and the linewidth enhancement factor in QD mode-locked lasers is addressed. The noise performance of two-section mode-locked lasers and a SOA-based ring laser was investigated. Significant reduction of the timing jitter under hybrid mode-locked operation was achieved owing to more than one order of magnitude reduction of the linewidth in QD gain media. Ultralow phase noise performance (integrated timing jitter of a few fs at a 10 GHz repetition rate) was demonstrated from an actively mode-locked unidirectional ring laser. These results show that quantum dot mode-locked lasers are strong competitors to conventional semiconductor lasers in noise performance. Finally we demonstrated an opto-electronic oscillator (OEO) and coupled opto-electronic oscillators (COEO) which have the potential for both high purity microwave and low noise optical pulse generation. The phase noise of the COEO is measured by the photonic delay line frequency discriminator method. Based on this study we discuss the prospects of the COEO as a low noise optical pulse source

    LOW PHASE NOISE CMOS PLL FREQUENCY SYNTHESIZER DESIGN AND ANALYSIS

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    The phase-locked loop (PLL) frequency synthesizer is a critical device of wireless transceivers. It works as a local oscillator (LO) for frequency translation and channel selection in the transceivers but suffers phase noise including reference spurs. In this dissertation for lowing phase noise and power consumption, efforts are placed on the new design of PLL components: VCOs, charge pumps and sigma delta modulators. Based on the analysis of the VCO phase noise generation mechanism and improving on the literature results, a design-oriented phase noise model for a complementary cross-coupled LC VCO is provided. The model reveals the relationship between the phase noise performance and circuit design parameters. Using this phase noise model, an optimized 2GHz low phase noise CMOS LC VCO is designed, simulated and fabricated. The theoretical analysis results are confirmed by the simulation and experimental results. With this VCO phase noise model, we also design a low phase noise, low gain wideband VCO with the typical VCO gain around 100MHz/V. Improving upon literature results, a complete quantitative analysis of reference spur is given in this dissertation. This leads to a design of a charge pump by using a negative feedback circuit and replica bias to reduce the current mismatch which causes the reference spur. In addition, low-impedance charge/discharge paths are provided to overcome the charge pump current glitches which also cause PLL spurs. With a large bit-width high order sigma delta modulator, the fractional-N PLL has fine frequency resolution and fast locking time. Based on an analysis of sigma delta modulator models introduced in this dissertation, a 3rd-order MASH 1-1-1 digital sigma delta modulator is designed. Pipelining techniques and true single phase clock (TSPC) techniques are used for saving power and area. Included is the design of a fully integrated 2.4GHz §¢ fractional-N CMOS PLL frequency synthesizer. It takes advantage of a sigma delta modulator to get a very fine frequency resolution and a relatively large loop bandwidth. This frequency synthesizer is a 4th-order charge pump PLL with 26MHz reference frequency. The loop bandwidth is about 150KHz, while the whole PLL phase noise is about -120dBc/Hz at 1MHz frequency offset

    Architecture, Modeling, and Analysis of a Plasma Impedance Probe

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    Variations in ionospheric plasma density can cause large amplitude and phase changes in the radio waves passing through this region. Ionospheric weather can have detrimental effects on several communication systems, including radars, navigation systems such as the Global Positioning Sytem (GPS), and high-frequency communications. As a result, creating models of the ionospheric density is of paramount interest to scientists working in the field of satellite communication. Numerous empirical and theoretical models have been developed to study the upper atmosphere climatology and weather. Multiple measurements of plasma density over a region are of marked importance while creating these models. The lack of spatially distributed observations in the upper atmosphere is currently a major limitation in space weather research. A constellation of CubeSat platforms would be ideal to take such distributed measurements. The use of miniaturized instruments that can be accommodated on small satellites, such as CubeSats, would be key to acheiving these science goals for space weather. The accepted instrumentation techniques for measuring the electron density are the Langmuir probes and the Plasma Impedance Probe (PIP). While Langmuir probes are able to provide higher resolution measurements of relative electron density, the Plasma Impedance Probes provide absolute electron density measurements irrespective of spacecraft charging. The central goal of this dissertation is to develop an integrated architecture for the PIP that will enable space weather research from CubeSat platforms. The proposed PIP chip integrates all of the major analog and mixed-signal components needed to perform swept-frequency impedance measurements. The design\u27s primary innovation is the integration of matched Analog-to-Digital Converters (ADC) on a single chip for sampling the probes current and voltage signals. A Fast Fourier Transform (FFT) is performed by an off-chip Field-Programmable Gate Array (FPGA) to compute the probes impedance. This provides a robust solution for determining the plasma impedance accurately. The major analog errors and parametric variations affecting the PIP instrument and its effect on the accuracy and precision of the impedance measurement are also studied. The system clock is optimized in order to have a high performance ADC. In this research, an alternative clock generation scheme using C-elements is described to reduce the timing jitter and reference spurs in phase locked loops. While the jitter performance and reference spur reduction is comparable with prior state-of-the-art work, the proposed Phase Locked Loop (PLL) consumes less power with smaller area than previous designs

    Challenges in the Locomotion of Self-Reconfigurable Modular Robots

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    Self-Reconfigurable Modular Robots (SRMRs) are assemblies of autonomous robotic units, referred to as modules, joined together using active connection mechanisms. By changing the connectivity of these modules, SRMRs are able to deliberately change their own shape in order to adapt to new environmental circumstances. One of the main motivations for the development of SRMRs is that conventional robots are limited in their capabilities by their morphology. The promise of the field of self-reconfigurable modular robotics is to design robots that are robust, self-healing, versatile, multi-purpose, and inexpensive. Despite significant efforts by numerous research groups worldwide, the potential advantages of SRMRs have yet to be realized. A high number of degrees of freedom and connectors make SRMRs more versatile, but also more complex both in terms of mechanical design and control algorithms. Scalability issues affect these robots in terms of hardware, low-level control, and high-level planning. In this thesis we identify and target three major challenges: (i) Hardware design; (ii) Planning and control; and, (iii) Application challenges. To tackle the hardware challenges we redesigned and manufactured the Self-Reconfigurable Modular Robot Roombots to meet desired requirements and characteristics. We explored in detail and improved two major mechanical components of an SRMR: the actuation and the connection mechanisms. We also analyzed the use of compliant extensions to increase locomotion performance in terms of locomotion speed and power consumption. We contributed to the control challenge by developing new methods that allow an arbitrary SRMR structure to learn to locomote in an efficient way. We defined a novel bio-inspired locomotion-learning framework that allows the quick and reliable optimization of new gaits after a morphological change due to self-reconfiguration or human construction. In order to find new suitable application scenarios for SRMRs we envision the use of Roombots modules to create Self-Reconfigurable Robotic Furniture. As a first step towards this vision, we explored the use and control of Plug-n-Play Robotic Elements that can augment existing pieces of furniture and create new functionalities in a household to improve quality of life

    Frequency Synthesizers and Oscillator Architectures Based on Multi-Order Harmonic Generation

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    Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply

    Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors

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    University of Minnesota Ph.D. dissertation.November 2016. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); x, 137 pages.Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V

    Heterogeneous Integration for Reduced Phase Noise and Improved Reliability of Semiconductor Lasers

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    Significant savings in cost, power and space are possible in existing optical data transmission networks, sensors and metrology equipment through photonic integration. Photonic integration can be broadly classified into two categories, hybrid and monolithic integration. The former involves assembling multiple single functionality optical devices together into a single package including any optical coupling and/or electronic connections. On the other hand monolithic integration assembles many devices or optical functionalities on a single chip so that all the optical connections are on chip and require no external alignment. This provides a substantial improvement in reliability and simplifies testing. Monolithic integration has been demonstrated on both indium phosphide (InP) and silicon (Si) substrates. Integration on larger 300mm Si substrates can further bring down the cost and has been a major area of research in recent years. Furthermore, with increasing interest from industry, the hybrid silicon platform is emerging as a new technology for integrating various active and passive optical elements on a single chip. This is both in the interest of bringing down manufacturing cost through scaling along with continued improvement in performance and to produce multi-functional photonic integrated circuits (PIC).The goal of this work is twofold. First, we show four laser demonstrations that use the hybrid silicon platform to lower phase noise due to spontaneous emission, based on the following two techniques, viz. confinement factor reduction and negative optical feedback. The first two demonstrations are of mode-locked lasers and the next two are of tunable lasers. Some of the key results include; (a) 14dB white frequency noise reduction of a 20GHz radio-frequency (RF) signal from a harmonically mode-locked long cavity laser with greater than 55dB supermode noise suppression, (b) 8dB white frequency noise reduction from a colliding pulse mode-locked laser by reducing the number of quantum wells and a further 6dB noise reduction using coherent photon seeding from long on-chip coupled cavity, (c) linewidth reduction of a tunable laser down to 160kHz using negative optical feedback from coupled ring resonator mirrors, and (d) linewidth reduction of a widely tunable laser down to 50kHz using on-chip coupled cavity feedback effect.Second, we present the results of a reliability study conducted to investigate the influence of molecular wafer bonding between Si and InP on the lifetime of distributed feedback lasers, a common laser source used in optical communication. No degradation in lasing threshold or slope efficiency was observed after aging the lasers for 5000hrs at 70°C and 2500hrs at 85°C. However, among the three chosen bonding interface layer options, the devices with an interface superlattice layer showed a higher yield for lasers and lower dark current values in the on-chip monitor photodiodes after aging
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