Video Processing Acceleration using Reconfigurable Logic and Graphics Processors

A vexing question is `which architecture will prevail as the core feature of the next state of the art video processing system?' This thesis examines the substitutive and collaborative use of the two alternatives of the reconfigurable logic and graphics processor architectures. A structured approach to executing architecture comparison is presented - this includes a proposed `Three Axes of Algorithm Characterisation' scheme and a formulation of perfor- mance drivers. The approach is an appealing platform for clearly defining the problem, assumptions and results of a comparison. In this work it is used to resolve the advanta- geous factors of the graphics processor and reconfigurable logic for video processing, and the conditions determining which one is superior. The comparison results prompt the exploration of the customisable options for the graphics processor architecture. To clearly define the architectural design space, the graphics processor is first identifed as part of a wider scope of homogeneous multi-processing element (HoMPE) architectures. A novel exploration tool is described which is suited to the investigation of the customisable op- tions of HoMPE architectures. The tool adopts a systematic exploration approach and a high-level parameterisable system model, and is used to explore pre- and post-fabrication customisable options for the graphics processor. A positive result of the exploration is the proposal of a reconfigurable engine for data access (REDA) to optimise graphics processor performance for video processing-specific memory access patterns. REDA demonstrates the viability of the use of reconfigurable logic as collaborative `glue logic' in the graphics processor architecture

Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

Modeling, Control and Estimation of Reconfigurable Cable Driven Parallel Robots

The motivation for this thesis was to develop a cable-driven parallel robot (CDPR) as part of a two-part robotic device for concrete 3D printing. This research addresses specific research questions in this domain, chiefly, to present advantages offered by the addition of kinematic redundancies to CDPRs. Due to the natural actuation redundancy present in a fully constrained CDPR, the addition of internal mobility offers complex challenges in modeling and control that are not often encountered in literature. This work presents a systematic analysis of modeling such kinematic redundancies through the application of reciprocal screw theory (RST) and Lie algebra while further introducing specific challenges and drawbacks presented by cable driven actuators. It further re-contextualizes well-known performance indices such as manipulability, wrench closure quality, and the available wrench set for application with reconfigurable CDPRs. The existence of both internal redundancy and static redundancy in the joint space offers a large subspace of valid solutions that can be condensed through the selection of appropriate objective priorities, constraints or cost functions. Traditional approaches to such redundancy resolution necessitate computationally expensive numerical optimization. The control of both kinematic and actuation redundancies requires cascaded control frameworks that cannot easily be applied towards real-time control. The selected cost functions for numerical optimization of rCDPRs can be globally (and sometimes locally) non-convex. In this work we present two applied examples of redundancy resolution control that are unique to rCDPRs. In the first example, we maximize the directional wrench ability at the end-effector while minimizing the joint torque requirement by utilizing the fitness of the available wrench set as a constraint over wrench feasibility. The second example focuses on directional stiffness maximization at the end-effector through a variable stiffness module (VSM) that partially decouples the tension and stiffness. The VSM introduces an additional degrees of freedom to the system in order to manipulate both reconfigurability and cable stiffness independently. The controllers in the above examples were designed with kinematic models, but most CDPRs are highly dynamic systems which can require challenging feedback control frameworks. An approach to real-time dynamic control was implemented in this thesis by incorporating a learning-based frameworks through deep reinforcement learning. Three approaches to rCDPR training were attempted utilizing model-free TD3 networks. Robustness and safety are critical features for robot development. One of the main causes of robot failure in CDPRs is due to cable breakage. This not only causes dangerous dynamic oscillations in the workspace, but also leads to total robot failure if the controllability (due to lack of cables) is lost. Fortunately, rCDPRs can be utilized towards failure tolerant control for task recovery. The kinematically redundant joints can be utilized to help recover the lost degrees of freedom due to cable failure. This work applies a Multi-Model Adaptive Estimation (MMAE) framework to enable online and automatic objective reprioritization and actuator retasking. The likelihood of cable failure(s) from the estimator informs the mixing of the control inputs from a bank of feedforward controllers. In traditional rigid body robots, safety procedures generally involve a standard emergency stop procedure such as actuator locking. Due to the flexibility of cable links, the dynamic oscillations of the end-effector due to cable failure must be actively dampened. This work incorporates a Linear Quadratic Regulator (LQR) based feedback stabilizer into the failure tolerant control framework that works to stabilize the non-linear system and dampen out these oscillations. This research contributes to a growing, but hitherto niche body of work in reconfigurable cable driven parallel manipulators. Some outcomes of the multiple engineering design, control and estimation challenges addressed in this research warrant further exploration and study that are beyond the scope of this thesis. This thesis concludes with a thorough discussion of the advantages and limitations of the presented work and avenues for further research that may be of interest to continuing scholars in the community

Automated optimization of reconfigurable designs

Currently, the optimization of reconfigurable design parameters is typically done manually and often involves substantial amount effort. The main focus of this thesis is to reduce this effort. The designer can focus on the implementation and design correctness, leaving the tools to carry out optimization. To address this, this thesis makes three main contributions. First, we present initial investigation of reconfigurable design optimization with the Machine Learning Optimizer (MLO) algorithm. The algorithm is based on surrogate model technology and particle swarm optimization. By using surrogate models the long hardware generation time is mitigated and automatic optimization is possible. For the first time, to the best of our knowledge, we show how those models can both predict when hardware generation will fail and how well will the design perform. Second, we introduce a new algorithm called Automatic Reconfigurable Design Efficient Global Optimization (ARDEGO), which is based on the Efficient Global Optimization (EGO) algorithm. Compared to MLO, it supports parallelism and uses a simpler optimization loop. As the ARDEGO algorithm uses multiple optimization compute nodes, its optimization speed is greatly improved relative to MLO. Hardware generation time is random in nature, two similar configurations can take vastly different amount of time to generate making parallelization complicated. The novelty is efficient use of the optimization compute nodes achieved through extension of the asynchronous parallel EGO algorithm to constrained problems. Third, we show how results of design synthesis and benchmarking can be reused when a design is ported to a different platform or when its code is revised. This is achieved through the new Auto-Transfer algorithm. A methodology to make the best use of available synthesis and benchmarking results is a novel contribution to design automation of reconfigurable systems.Open Acces

Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style

High-level synthesis (HLS) has been researched for decades and is still limited to fast FPGA prototyping and algorithmic RTL generation. A feasible end-to-end system-level synthesis solution has never been rigorously proven. Modularity and composability are the keys to enabling such a system-level synthesis framework that bridges the huge gap between system-level specification and physical level design. It implies that 1) modules in each abstraction level should be physically composable without any irregular glue logic involved and 2) the cost of each module in each abstraction level is accurately predictable. The ultimate reasons that limit how far the conventional HLS can go are precisely that it cannot generate modular designs that are physically composable and cannot accurately predict the cost of its design. In this paper, we propose Vesyla, not as yet another HLS tool, but as a synthesis tool that positions itself in a promising end-to-end synthesis framework and preserving its ability to generate physically composable modular design and to accurately predict its cost metrics. We present in the paper how Vesyla is constructed focusing on the novel platform it targets and the internal data structures that highlights the uniqueness of Vesyla. We also show how Vesyla will be positioned in the end-to-end synchoros synthesis framework called SiLago

Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

Active and Passive Multi-Sensor Radar Imaging Techniques Exploiting Spatial Diversity

The work here presented reports several innovative SAR and ISAR radar imaging techniques exploiting the spatial diversity offered by multi-sensor systems in order to improve the performance with respect to the conventional, single channel cases. Both the cases of dedicated transmitters and exploitation of opportunity transmitters are considered

Active and Passive Multi-Sensor Radar Imaging Techniques Exploiting Spatial Diversity

The work here presented reports several innovative SAR and ISAR radar imaging techniques exploiting the spatial diversity offered by multi-sensor systems in order to improve the performance with respect to the conventional, single channel cases. Both the cases of dedicated transmitters and exploitation of opportunity transmitters are considered