On the experimental verification of quantum complexity in linear optics

The first quantum technologies to solve computational problems that are beyond the capabilities of classical computers are likely to be devices that exploit characteristics inherent to a particular physical system, to tackle a bespoke problem suited to those characteristics. Evidence implies that the detection of ensembles of photons, which have propagated through a linear optical circuit, is equivalent to sampling from a probability distribution that is intractable to classical simulation. However, it is probable that the complexity of this type of sampling problem means that its solution is classically unverifiable within a feasible number of trials, and the task of establishing correct operation becomes one of gathering sufficiently convincing circumstantial evidence. Here, we develop scalable methods to experimentally establish correct operation for this class of sampling algorithm, which we implement with two different types of optical circuits for 3, 4, and 5 photons, on Hilbert spaces of up to 50,000 dimensions. With only a small number of trials, we establish a confidence >99% that we are not sampling from a uniform distribution or a classical distribution, and we demonstrate a unitary specific witness that functions robustly for small amounts of data. Like the algorithmic operations they endorse, our methods exploit the characteristics native to the quantum system in question. Here we observe and make an application of a "bosonic clouding" phenomenon, interesting in its own right, where photons are found in local groups of modes superposed across two locations. Our broad approach is likely to be practical for all architectures for quantum technologies where formal verification methods for quantum algorithms are either intractable or unknown.Comment: Comments welcom

SVtL: System Verification through Logic: tool support for verifying sliced hierarchical statecharts

SVtL is the core of a slicing-based verification environment for UML statechart models. We present an overview of the SVtL software architecture. Special attention is paid to the slicing approach. Slicing reduces the complexity of the verification approach, based on removing pieces of the model that are not of interest during verification. In [18] a slicing algorithm has been proposed for statecharts, but it was not able to handle orthogonal regions efficiently. We optimize this algorithm by removing false dependencies, relying on the broadcasting mechanism between different parts of the statechart model

A formal methodology for integral security design and verification of network protocols

We propose a methodology for verifying security properties of network protocols at design level. It can be separated in two main parts: context and requirements analysis and informal verification; and formal representation and procedural verification. It is an iterative process where the early steps are simpler than the last ones. Therefore, the effort required for detecting flaws is proportional to the complexity of the associated attack. Thus, we avoid wasting valuable resources for simple flaws that can be detected early in the verification process. In order to illustrate the advantages provided by our methodology, we also analyze three real protocols

Verifying the Safety of a Flight-Critical System

This paper describes our work on demonstrating verification technologies on a flight-critical system of realistic functionality, size, and complexity. Our work targeted a commercial aircraft control system named Transport Class Model (TCM), and involved several stages: formalizing and disambiguating requirements in collaboration with do- main experts; processing models for their use by formal verification tools; applying compositional techniques at the architectural and component level to scale verification. Performed in the context of a major NASA milestone, this study of formal verification in practice is one of the most challenging that our group has performed, and it took several person months to complete it. This paper describes the methodology that we followed and the lessons that we learned.Comment: 17 pages, 5 figure

Hierarchical gate-level verification of speed-independent circuits

This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on the number of state signals (C elements, RS flip-flops) of the circuit. Despite the reduction to complex gates, verification is kept exact. The specification of the environment only requires to describe the transitions of the input/output signals of the circuit and is allowed to express choice and non-determinism. Experimental results obtained from circuits with more than 500 gates show that the computational cost can be drastically reduced when using hierarchical verification.Peer ReviewedPostprint (published version